UDC 681.5, 681.325.5 (075.8)
BBK 32.973.202-018.2 i 73
A. N. ShcherbinaComputing machines, systems and networks. Microcontrollers and microprocessors in control systems: cheb. allowance / A.N. Shcherbina, P.A. Nechaev- SPb .: From the Polytechnic. University, 2012.-226 p.
Corresponds to the content of the state educational standard for areas of training and specialties in the field of management in technical systems, electric power and electrical engineering and the content of the exemplary curriculum for the discipline "Computing machines, systems and networks."
The fundamental issues of the logical organization of microprocessor systems are considered on the example of the basic architecture of the MCS-51 microcontroller family from Intel. The technology of programming microcontrollers in Assembler and SI languages is described.
It can be useful for students and teachers of higher technical institutions, specialists in the automation of technological processes and production equipment, as well as for design engineers of microprocessor systems.
It also complies with the content of the state educational standard of disciplines "Microcontrollers and microprocessors in control systems" and "Electronic devices of automation" bachelor's, engineering and master's training in the direction 140400 "Electrical power engineering and electrical engineering".
Reprinted by the decision of the Editorial and Publishing Council
St. Petersburg State Polytechnic University.
© Shcherbina A. N., Nechaev P. A., 2012
© Saint Petersburg State
Polytechnic University, 2012
ISBN 978-5-7422-3553-8
Introduction .. 7
Chapter 1. Architecture of the MCS51 family. ten
1.1 General characteristics 10
1.2 Block diagram 11
1.3 Purpose of the conclusions of the microcontroller 8051 15
1.4 Memory organization 17
1.4.1 Program memory (ROM) 18
1.4.2 Data memory (RAM) 19
1.4.3 Registers of special functions. twenty
1.4.4 Flags Register (PSW) 23
1.5 Control and synchronization device 26
1.6 Arrangement of I / O Ports 27
1.6.1 General information. 27
1.6.2 Alternative functions. 27
1.7. Timers / Counters for 8051 microcontrollers.28
1.7.1. Timer-counters structure. 28
1.7.2 Modes of operation of timers-counters. thirty
1.8. Serial port 32
1.8.1. Serial port structure. 32
1.8.2. Transceiver control / status register SCON .. 34
1.8.3. Power control register PCON .. 36
1.9. Interrupt system 37
1.9.1. Interrupt system structure. 37
1.9.2 Execution of interrupt routines. 40
Chapter 2. Features of the 80C51GB microcontroller .. 42
2.1 Features 42
2.2 I / O Ports P0-P5 43
2.2.1 Functioning of the input-output ports. 43
2.2.2 Writing to Port .. 46
2.3 Features of the 8XC51GB interrupt system .. 49
Enable / disable interrupts. 50
Interrupt priority management. 51
External interrupts. 54
2.3. ADC Node 56
2.4. Hardware Watchdog 61
2.5. Clock Failure Detection 63
2.6. Matrix of programmable counters RSA 64
2.6.1. PCA structure .. 64
2.6.2. PCA counter mode register (CMOD) 66
2.6.3. PCA counter control register (CON) 67
2.6.4. Compare / commit modules. 68
2.7. Extended Serial Port 76
2.8. Timers / Counters 79
Pinout of microcontrollers group 8XC51GB .. 86
Chapter 3. Programming MK 8051GB .. 89
3.1. Programming Model 89
3.2 Data Types 93
3.3 Methods of data addressing 93
3.4 Command System 95
3.4.1 General characteristics. 95
3.4.2 Command types. 96
3.4.3 Types of operands. 97
3.4.4 Commands for transferring microcontroller data. 98
3.4.5 Commands for arithmetic operations 8051.101
3.4.6 Commands of logical operations of the microcontroller 8051.104
3.4.7 Commands for operations with bits of microcontroller 8051.106
3.5 Debugging Programs 111
Chapter 4. Programming language ASM-51. 112
4.2 Writing Program Text 113
4.3 The alphabet of the language. 114
4.4 Identifiers. 115
4.5 Numbers 117
4.6 Directives 118
4.7 Implementation of subroutines in ASM51 language 122
4.7.1 The structure of a subroutine-procedure in the ASM51 language. 122
4.7.2 Passing variable parameters to a subroutine. 123
4.7.3 Implementation of subroutine functions in ASM51 language. 123
4.7.4 Implementation of interrupt handling routines in ASM51 language. 124
4.8 Structured programming in assembly language. 125
4.9 Features of broadcasting multi-module programs. 126
4.10 Using segments 128
4.10.1 Splitting the MK memory into segments .. 128
4.10.2 Absolute memory segments. 129
4.10.2 Relocatable memory segments. 131
Chapter 5. Programming language С-51. 134
5.1 General characteristics of the language 134
5.3 Program structure С-51 136
5.3. Elements of the C-51 programming language 138
5.3.1. Symbols .. 138
5.3.2. Lexical units, separators and the use of spaces. 141
5.3.3 Identifiers .. 142
5.3.4 Keywords. 143
5.3.5 Constants .. 143
5.4. Expressions in Language Operators 146
programming C-51 146
5.5. Priorities for Operations 148
5.6. Operators of the C-51 programming language 149
5.6.1. Declaration operators. 150
5.6.2 Executable Operators .. 150
5.6.3 The assignment operator. 151
5.6.4 Conditional operator. 151
5.6.5 Structured operator (). 152
5.6.6 Loop operator for. 152
5.6.7 Operator of the loop with checking the condition up to the body of the while loop. 153
5.6.8 Operator of the loop with a check of the condition after the body of the loop do while. 154
5.6.9 Operator break. 155
5.6.10 Operator continue. 155
5.6.11 The operator of choice switch. 155
5.6.12 Operator of unconditional branch goto. 157
5.6.13 Operator expression. 158
5.6.14 Operator of return from subroutine return. 158
5.6.15 Empty statement. 158
5.7. Declaring variables in the C-51 programming language. 159
5.7.1. Variable declaration. 159
5.7.3 Integer data types. 161
5.7.4 Floating point numbers. 162
5.7.5 Variables of the enumerated type. 162
5.7.6. Declaring arrays in the C-51 programming language. 164
5.7.7. Structures .. 165
5.7.8. Combinations (mixtures) 166
5.8. Using Pointers in C-51 167
5.8.1. Declaration of pointers. 167
5.8.2. Untyped pointers. 168
5.8.3. Memory dependent pointers. 169
5.9. Declaring New Variable Types 169
5.10. Data initialization 170
5.11. Using subroutines in the C-51 programming language. 170
5.11.1. Defining subroutines. 171
5.11.2. Parameters of subroutines. 173
5.11.3. Pre-declaration of subroutines. 174
5.11.4 Calling subroutines .. 176
5.11.5 Recursive call of subroutines. 176
5.11.6 Interrupt handling routines. 177
5.11.7 Scopes of variables and subroutines. 178
5.12. Multimodal programs 179
Chapter 6. Preparing programs in the Keil μVision2 integrated development environment. 182
6.1 Creating a Project in ASM-51 Language 182
6.2 An example of creating a project in C for a training controller in the Keil μVision2 integrated development environment 188
Chapter 7. Description of the training controller .. 199
7.1. Controller structure 199
7.2. Address space 200
7.2.1. Memory allocation. 200
7.2.2 External memory. 201
7.2.3. Internal data memory. 202
7.3. I / O Port Mapping 202
7.4. Serial port ……………………………… ... 203
7.5. Working with LCD 205
7.6. Controller panels ………………………………………………… 213
APPENDIX P2 STRUCTURE OF THE LABORATORY REPORT …… ..217
Appendix A3 Codes of machine instructions. 217
References ... 224
Introduction
In the development of specialties related to the automation of technological processes and industries, the study of microcontrollers is one of the important sections.
There is a continuous development and the emergence of more and more 16- and 32-bit microcontrollers and microprocessors in the world, but the largest share of the world microprocessor market to this day remains with 8-bit devices. According to all forecasts of analytical companies for the near future, the leading position of 8-bit microcontrollers in the world market will remain.
Currently, among all 8-bit microcontrollers, the MCS-51 family is the undoubted leader in terms of the number of varieties and the number of companies producing its modifications. It got its name from the first representative of this family - the 8051 microcontroller. A successful set of peripheral devices, flexible choice of external or internal program memory and reasonable price ensured this microcontroller success in the market.
Advantages of the MCS-51 family:
· Architecture, which is the de facto standard;
· The extraordinary breadth of the family and the variety of possibilities;
· Availability of high-performance and extended versions of processors;
· A significant number of freely available software and hardware developments;
· Ease of hardware programming, including in-circuit programming;
· Low cost and availability of basic chips;
Availability of specialized versions of controllers for special conditions of use
· Availability of versions of controllers with a reduced level of electromagnetic interference;
· Widely known among the developers of the older generation, both in the world and in the CIS countries;
· Support of architecture by the world's leading educational institutions.
And finally, the main advantage: having mastered the basic chip of the family, you can easily start working with such computing "monsters" as microcontrollers Cygnal, Dallas Semiconductor, Analog Devices, Texas Instruments.
The MCS-51 family includes a range of microcircuits from the simplest microcontrollers to the most complex ones. To date, there are more than 200 modifications of the 8051 family of microcontrollers, produced by almost 20 companies. Every year, more and more variants of representatives of this family appear.
The main directions of development are:
· Increase in performance (increase in clock frequency and redesign of the architecture);
· Reduction of supply voltage and power consumption;
· An increase in the amount of RAM and FLASH memory on a chip with the possibility of in-circuit programming;
· Introduction of complex devices such as drive control systems, CAN and USB interfaces, etc. into the microcontroller periphery.
Microcontrollers of the MCS-51 family allow you to perform both control tasks for various devices, and implement individual nodes of an analog circuit. All microcircuits of this family work with the same instruction set. Most of them are made in the same cases with the same pinout (numbering of the legs for the case). This allows the use of microcircuits from different manufacturers for the developed device without altering the circuit diagram of the device and program.
The main manufacturers of varieties of the 51st family in the world are Philips, Siemens, Intel, Atmel, Dallas, Temic, Oki, AMD, MHS, Gold Star, Winbond, Silicon Systems and a number of others.
The characteristics of analogs of microcontrollers of the MCS-51 family (Intel 8XC51FA, 8XC51GB, 80C152) with extended capabilities are given in table. IN 1.
Table B.1
| RAM | ROM | PCA | ADC | WDT | T / C | Afterbirth. Channels | Peculiarities | |
| Atmel: AT89C2051 | ||||||||
| - | - | - | - | UART | Flash 2 Kb | |||
| AT89C4051 | - | - | - | - | UART | Flash 4Kb | ||
| AT89S4D12 | 128K | - | - | - | UART, SPI | Flash 4Kb | ||
| DALLAS Semiconductor: DS5000FP | ||||||||
| - | - | - | + | UART | Bootstrap loader | |||
| DS5001FP | - | - | - | + | UART | Bootstrap loader | ||
| DS8xC520 | 16K | - | - | + | 2xUART | 2 DPTR | ||
| SIEMENS: C505C | ||||||||
| 16K | - | + | + | UART, CAN | 8 DPTR | |||
| C515C | 64K | - | + | + | UART + SSC + CAN | 4 PWM, 8 DPTR | ||
| Philips: * 89C51RA + | ||||||||
| - | + | - | + | UART | 2 DPTR, 4 lv. interrupt, clock out, Flash 8K | |||
| P51XAG1x | 8K | - | - | + | 2 UART | |||
| Intel: 8xC51RA | ||||||||
| 8K | - | + | + | UART | 4 levels IRQ, clock out | |||
| 8XC196KC | 64K | 16K | - | + | - | UART | 3 PWM | |
| 80C196KB | 64K | 8K | - | + | - | UART | PWM |
Chapter 1. Architecture of MCS51 Family
The MCS-51 family of 8-bit single-chip microcontrollers have gained great popularity among microprocessor control system designers due to their well-designed architecture. Microcontroller architecture is a collection of internal and external software-accessible hardware resources and instruction systems. The architecture of the MCS-51 family is largely predetermined by its purpose - the construction of compact and cheap digital devices. Microcontrollers that perform all the functions of a microcomputer using a single microcircuit are called single-chip computers (OEVM).
Intel has released about 50 models based on the operating core of the Intel 8051 microcontroller. At the same time, many other firms, such as Atmel, Philips, began producing their own microcontrollers developed in the MCS-51 standard.
General characteristics
The main characteristics of the family:
· 8-bit central processing unit (CPU), focused on controlling executive devices;
· The CPU has a built-in circuit for 8-bit hardware multiplication and division of numbers;
· The presence in the instruction set of a large number of operations for working with directly addressable bits makes it possible to talk about a processor for working with bit data (boolean processor);
· Internal (located on the chip) program memory of a masked or reprogrammed type, which for various crystals has a volume of 4 to 32 Kb, in some versions it is absent;
· Not less than 128 bytes resident data RAM, which is used for organization, register banks, stack and storage of user data;
· At least 32 bidirectional interface lines (ports), individually configured for input or output of information;
· Two 16-bit multi-mode counters / timers used to count external events, organize time delays and clock the communication port;
· Bi-directional duplex asynchronous transceiver (UART), designed to organize communication channels between the microcontroller and external devices with a wide range of information transfer rates. There are tools for hardware and software integration of microcontrollers into a connected system;
· Two-level priority interrupt system that supports at least 5 vectors of interrupts from 4 internal and 2 external sources of events;
· Built-in clock generator.
Structural scheme
The block diagram of the controller is shown in Fig. 1.1 and consists of the following main functional units: control unit, arithmetic logic device, timer / counter unit, serial interface and interrupt unit, program counter, data memory and program memory. Bidirectional exchange is carried out using an internal 8-bit data highway. Almost all representatives of the MCS-51 family are built according to this scheme. Various microcircuits of this family differ only in special-purpose registers (including the number of ports).
Timing and Control Unit- designed to generate synchronizing and control signals that ensure the coordination of the joint operation of the OEVM units in all permissible modes of its operation. The control unit includes:
a device for forming time intervals;
I / O logic;
register of commands;
electricity consumption control register;
decoder of commands, computer control logic.
Rice. 1.1. Block diagram of the I8051 controller.
Time slot shaping device is intended for the formation and issuance of internal sync signals of phases, clocks and cycles. The number of machine cycles determines the duration of the instruction execution. Almost all OEVM commands are executed in one or two machine cycles, except for multiplication and division commands, the duration of which is four machine cycles. Let us designate the frequency of the master oscillator by F g. The duration of the machine cycle is 12 / F g or 12 periods of the signal of the master oscillator. The input-output logic is designed to receive and issue signals that provide information exchange with external devices through the P0-P3 input / output ports.
Command register is intended for recording and storing the 8-bit operation code of the command being executed. The operation code, with the help of a command decoder and computer control logic, is converted into a microprogram for command execution.
Consumption Control Register (PCON) allows you to stop the microcontroller to reduce power consumption and reduce the level of noise from the microcontroller. Further reduction of power consumption and noise reduction can be achieved by stopping the master oscillator of the microcontroller. This can be achieved by flipping a bit in the Consumption Control Register PCON. For n-MOS (1816 series or foreign microcircuits with no "c" in the middle), the PCON Consumption Control Register contains only one bit that controls the SMOD serial port baud rate, and there are no power control bits.
Arithmetic Logic Unit (ALU) is a parallel eight-bit device that performs arithmetic and logical operations. ALU consists of:
accumulator registers, holding registers TMP1 and TMP2;
ROM of constants;
adder;
additional register (register B);
battery (ACC);
program status register (PSW).
Register accumulator and holding registers- eight-bit registers intended for receiving and storing operands for the duration of operations on them. These registers are not programmatically accessible.
ROM constants provides the generation of a correction code for binary-decimal data representation, a mask code for bit operations and a constant code.
Parallel eight-bit adder is a combination-type circuit with sequential carry, designed to perform arithmetic operations of addition, subtraction and logical operations of addition, multiplication, unequal and identical.
Register B- an eight-bit register used during multiplication and division operations. For other instructions, it can be viewed as an additional super-operative register.
Battery- an eight-bit register designed to receive and store the result obtained when performing arithmetic-logical operations or shift operations
Serial interface and interrupt unit (PIP) is intended for the organization of input - output of sequential streams of information and the organization of a system for interrupting programs. The block includes:
PIP buffer;
control logic;
control register;
transmitter buffer;
receiver buffer;
serial port transceiver;
interrupt priority register;
interrupt enable register;
interrupt flag processing logic and vector generation circuit.
Program Counter is designed to form the current 16-bit address of the internal program memory and the 8/16-bit address of the external program memory. The instruction counter includes a 16-bit PC buffer, a PC register, and an increment circuit (increasing the content by 1).
Data memory (RAM) is intended for temporary storage of information used in the process of program execution.
Ports P0, P1, P2, P3 are quasi-bidirectional input-output ports and are designed to ensure the exchange of information between the computer and external devices, forming 32 input-output lines.
Program Status Register (PSW) intended for storing information about the state of the ALU during program execution.
Program memory (EPROM) is intended for storing programs and is a read-only memory (ROM). Different microcircuits use mask, UV-erasable or FLASH ROM.
Data Pointer Register (DPTR) is designed to store a 16 - bit address of external data memory.
Stack Pointer (SP) is an eight-bit register designed to organize a special area of data memory (stack), in which any memory cell can be temporarily stored.
1.3 Purpose of the conclusions of the microcontroller 8051(fig. 1.2)
· U ss - potential of the common wire ("ground");
· U cc - main supply voltage +5 V;
· X1, X2 - leads for connecting a quartz resonator;
RST - microcontroller general reset input;
PSEN - permission of the external program memory, issued only when accessing the external ROM;
· ALE - strobe of the external memory address;
· ЕА - disable internal program memory; level 0 at this input forces the microcontroller to execute the program only from the external ROM; ignoring the internal (if the latter is available);
Rice. 1.2. Pin assignment 8051.
· P1 - eight-bit quasi-bidirectional input / output port, each bit of the port can be programmed both for input and output of information, regardless of the state of other bits;
· P2 - an eight-bit quasi-bi-directional port, similar to P1, the pins of this port are used to issue address information when accessing external program or data memory (if the latter is 16-bit addressing). In addition, the pins of the port are used during programming to enter the high-order bits of the address into the microcontroller;
РЗ - an eight-bit quasi-bidirectional port, similar to P1, the pins of this port can perform a number of alternative functions that are used when operating timers, a serial input-output port, an interrupt controller, and external program and data memory;
· P0 - multiplexed eight-bit bidirectional information input-output port, through this port at different times the low byte of the address and data are output.
Organization of memory
The entire MCS-51 series has a Harvard architecture, that is, separate address spaces for program memory and data. The memory structure is shown in Fig. 1.3.
The amount of internal (resident) program memory (ROM, EPROM or OTP ROM) located on the chip, depending on the type of microcircuit, can be 0 (ROMless), 4K (base crystal), 8K, 16K or 32K. If necessary, the user can expand the program memory by installing an external ROM. Access to the internal or external ROM is determined by the value of the signal at the EA pin (External Access):
EA = V cc (supply voltage) - access to the internal ROM;
EA = V ss (ground potential) - access to external ROM.
For crystals without ROM (ROMless), the EA pin must be permanently connected to V ss.
 |  |
Rice. 1.3. Memory organization of the MCS-51 family
External ROM read strobe - (Program Store Enable) is generated when accessing the external program memory and is inactive during access to the ROM located on the chip. The area of the lower addresses of the program memory is used by the interrupt system. The architecture of the base 8051 chip provides support for five interrupt sources:
· Two external interrupts;
· Two interrupts from timers;
· Interrupts from the serial port.
In fig. 1.4 shows a map of the lower area of program memory.
Rice. 1.4. Lower program memory map
Program memory (ROM)
In microcontrollers of the 8051 family, the program memory and data memory are independent and independent from each other devices, addressed by various commands and control signals.
The built-in program memory located on the chip of the 8051 microcontroller is 4 KB (in the family up to 32). When accessing external program memory, all microcontrollers of the 8051 family always use a 16-bit address, which provides them with access to 64 KB of ROM. The microcontroller accesses program memory when reading the opcode and operands (using the PC instruction counter), as well as when executing instructions to copy a byte from program memory to the battery. When copying data commands are executed, the addressing of the program memory cell from which data will be read can be carried out using both the PC counter and the special two-byte DPTR data pointer register.
Data memory (RAM)
The amount of on-chip data memory is 128 bytes. The external data memory can be up to 64KB. The first 32 bytes are organized into four banks of general-purpose registers, designated respectively bank 0 - bank 3. Each of them consists of eight registers R0 – R7. At any time, the program is available, with register addressing, only one bank of registers, the number of which is contained in the third and fourth bits of the status word of the PSW program.
8051 microcontroller memory bit area addresses
Table 1.1
| Byte address (Hex) | Bit addresses by bit | |||||||
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
| 2F | 7F | 7E | 7D | 7C | 7B | 7A | ||
| 2E | ||||||||
| 2D | 6F | 6E | 6D | 6C | 6B | 6A | ||
| 2C | ||||||||
| 2B | 5F | 5E | 5D | 5C | 5B | 5A | ||
| 2A | ||||||||
| 4F | 4E | 4D | 4C | 4B | 4A | |||
| 3F | 3E | 3D | 3C | 3B | 3A | |||
| 2F | 2E | 2D | 2C | 2B | 2A | |||
| 1F | 1E | 1D | 1C | 1B | 1A | |||
| 0F | 0E | 0D | 0C | 0B | 0A | |||
| 20h |
The remaining address space can be configured by the developer at his discretion: it can accommodate the stack, system and user data areas. Data memory cells can be accessed in two ways. The first way is direct addressing of a memory cell. In this case, the cell address is the operand of the corresponding instruction. The second method is indirect addressing using the R0 or R1 pointer registers: before executing the corresponding command, the address of the cell to be addressed must be entered into one of them.
To access external data memory, only indirect addressing is used using the R0 and R1 registers or using the 16-bit DPTR pointer register.
Part of the data memory is a bit area, in which it is possible, with the help of special bit instructions, to address each bit of memory cells. The address of directly addressable bits can also be written as (ByteAddress). (Bit). The correspondence of these two addressing methods can be determined from the table. 1.1.
- Arithmetic commands;
- Logical commands;
- Data transfer commands;
- Bit processor commands;
- Branching and control transfer commands.
- Register addressing
- Direct addressing
- Indirect register addressing
- Direct addressing
- Indirect register addressing by the sum of the base and index registers
| Designation, symbol | Appointment |
| A | Battery |
| Rn | Registers of the currently selected register bank |
| r | The number of the loaded register specified in the command |
| direct | Directly addressable 8-bit internal data cell address, which can be an internal data RAM cell (0-127) or SFR (128-255) |
| @Rr | Indirectly addressable 8-bit cell of internal data RAM |
| data8 | 8-bit direct data going to the CPC |
| dataH | Most significant bits (15-8) of direct 16-bit data |
| dataL | Least significant bits (7-0) of direct 16-bit data |
| addr11 | 11-bit destination address |
| addrL | The least significant bits of the destination address |
| disp8 | 8-bit byte offset with sign m |
| bit | Direct addressable bit whose address contains the CPC located in the internal data RAM or SFR |
| a15, a14 ... a0 | Destination address bits |
| (NS) | Content of element X |
| ((NS)) | Content at the address stored in element X |
| (X) [M] | Discharge M of element X |
| + - * / AND OR XOR / X | Operations: addition subtraction multiplication division logical multiplication (AND operation) logical addition (OR operation) modulo 2 addition (exclusive OR) inversion of the element X |
Function mnemonics are uniquely associated with specific combinations of addressing methods and data types. A total of 111 such combinations are possible in the command system. The table provides a list of commands, sorted alphabetically.
| Mnemonics | Function | Flags |
| ACALL Command | Absolute subroutine call | |
| ADD Team A,<байт-источник> | Addition | AC, C, OV |
| ADDC Team A,<байт-источник> | Carry folding | AC, C, OV |
| AJMP Team | Absolute transition | |
| ANL Team<байт-назначения>, <байт-источникa> | Logical "AND" | |
| ANL C Team,<байт-источникa> | Logical "AND" for variable bits | |
| CJNE Team<байт-назначения>, <байт-источник>, <смещение> | Compare and jump if not equal | C |
| CLR A Command | Battery reset | |
| CLR Command | Clearing a bit | C, bit |
| CPL Team A | Inversion of ak umul ora | |
| CPL Team | Bit inversion | C, bit |
| Team DA A | Accumulator decimal correction for insertion | AC, C |
| DEC Team<байт> | Decrement | |
| DIV AB Team | Division | C, OV |
| DJNZ Team<байт>, <смещение> | Decrement and transition if not zero | |
| INC Team<байт> | Increment | |
| INC DPTR Team | Data Pointer Increment | |
| JB Team | Jump if bit is set | |
| JBC Team | Jump if a bit is set and clear that bit | |
| JC Team | Jump if carry is set | |
| JMP @ A + DPTR Command | Indirect transition | |
| JNB Team | Jump if bit is not set | |
| JNC Team | Jump if carry is not set | |
| JNZ Team | Jump if battery content is non-zero | |
| JZ Team | Jump if accumulator content is 0 | |
| LCALL Command | Long call | |
| LJMP Team | Long crossing | |
| MOV command<байт-назначения>, <байт-источника> | Send variable-byte | |
| MOV command<бит-назначения>, <бит-источника> | Send data bit | C |
| MOV DPTR command, # data16 | Load Data Pointer With 16-Bit Constant | |
| MOVC command A, @ A + ( | Send byte from program memory | |
| MOVX command<байт приемника>, <байт источника> | Send data to external memory (from external memory) | |
| MUL AB Team | Multiplication | C, OV |
| NOP command | No operation | PC |
| ORL Team<байт-назначения>, <байт-источникa> | Logical "OR" for variable-bytes | |
| ORL C Team,<бит источникa> | Logical "OR" for variable bits | C |
| POP command | Reading from the stack | |
| PUSH command | Stacking | |
| RET command | Return from subroutine | |
| RETI team | Return from interrupt | |
| RL A Team | Shift battery contents to the left | |
| RLC A Team | Shift battery contents to the left via carry flag | |
| Team RR A | Shift battery contents to the right | |
| RRC A Team | Shift battery contents to the right via carry flag | C |
| SETB command | Set bit | C |
| SJMP Team<метка> | Short jump | |
| SUBB A team,<байт источника> | Subtraction with a loan | AC, C, OV |
| SWAP A Command | Exchange of notebooks inside the battery | |
| Team XCH A,<байт> | Swapping the contents of a variable-byte accumulator | |
| XCHD Team A, @ R1 | Exchanging a notebook | |
| XRL Command<байт-назначения>, <байт-источникa> | Logical EXCLUSIVE OR for variable-bytes |
Microcontrollers of the MCS-51 family are built according to the Harvard architecture, in which the program memory and data memory are partitioned, have their own address spaces and ways of accessing them.
Program memory
The maximum amount of memory is 64K bytes, of which 4K, 8K, 16K or 32K bytes of memory (Table 7.3.1) are located on the chip, the rest is outside the die.
With voltage at terminal EA =
V CC
both internal and external memory are used, with EA = V CC = 0 - only external memory.
Table 7.3.1 shows program memory addresses for the indicated cases.
The lower area of the program memory is allocated for starting the microcontroller (starting address 0000h after reset) and for processing interrupts (interrupt addresses are located with an interval of 8 bytes: 0003h, 000Bh, 0013h, etc.).
The program memory is read-only, and when accessed:
● to external memory programs, the ¯PSEN signal is generated and a 16-bit address is always formed.
The low byte of the address is transmitted through port P0 in the first half of the machine cycle and is fixed at the edge of the ALE strobe in the register.
In the second half of the cycle, port P0 is used to enter a byte of data from external memory into the MC.
The high-order byte of the address is transmitted through the P2 port during the entire memory access time (Fig. 7.1.11);
● to internal memory the read signal is not generated and exchange cycles are used on the internal bus of the microcontroller.
Data memory
Internal memory data can be conditionally divided into three blocks (Table 7.3.2). 
The internal memory is always addressed by a byte, which only addresses 256 memory locations.
Therefore, as can be seen from Table 7.3.2, for addressing the upper 8-bit cells of the internal RAM and registers of special functions SFR, occupying the same address space, the commands use different addressing methods: indirect and straight.
Features of the organization of the lower area of internal RAM are reflected in table 7.3.3.
Low 32 bytes of internal RAM with addresses 00h.
1Fh are grouped into four banks with eight registers each (R0.R7).
Next 16 bytes of RAM with 20h addresses.
2Fh represent a memory area of 8 × 16 = 128 bits, which allows each individual bit to be accessed.
To select the address of the bank register, its name R0 is used.
R7, to select a bank - bits RS0, RS1 of the PSW status word register.
Bit addresses
Bit addresses are given in Table 7.3.3.
Addressing is carried out direct way. 
A list of all registers of special functions SFR with their addresses is given in Table 7.2.2.
For clarity, in table 7.3.
4 shows register address mapSFR of the considered microcircuits of the MCS-51 family.
The SFR address is determined by a combination of column and line numbers in hexadecimal notation.
For example, the CMOD register has the address D9h. 
For SFR registers whose addresses end in 0h or 8h (they are in bold), in addition to byte allowed bitwise addressing.
In this case, the address of the bit occupying the Nth bit in the register is defined as XXh + 0Nh, where XXh is the address of the SFR register, N = 0.7.
Bit addresses in this area range from 80H to FFH.
For example, the bit addresses of the ACC accumulator lie within the range E0h-E7h.
External memory data (up to 64 KB) is created by additional memory chips that are connected to the MC.
To work with external data memory, special commands are used, so the address spaces of external and internal memory do not overlap and, therefore, both types of data memory can be used simultaneously.
To access the cells of external data memory are used (Figure 7.1.8):
● commands with indirect addressing;
● signals for reading ¯RD and writing ¯WR;
● port P0 for transmitting the least significant byte of the address and receiving / transmitting the data byte;
● P2 port for transmitting the high-order byte of the address.
Addressing methods.
The command system uses:
● direct, indirect, register, indirect-register, direct and index addressing (indirect addressing by the sum of the base and index registers) source operands;
● direct, register and indirect-register addressing destination operands.
The combination of these methods (addressing) provides 21 addressing modes.
This command system and the tables below use the following notation:
Direct addressing.
With this addressing method, the location of the byte or data bit is determined by the 8-bit address of the second (and third) command byte.
Direct addressing is only used to access the internal data memory (lower 128 bytes of RAM) and special function registers.
Register addressing.
This addressing method provides access to data stored in one of the eight R0 registers.
R7 of the current bank of working registers.
It can also be used to access registers A, B, AB (dual register), DPTR pointer register, and carry flag C.
The address of these registers is embedded in the operation code, thereby reducing the number of command bytes.
Indirect register addressing.
In this case, the address of the data is stored in a pointer register, the location of which is determined by the operation code.
This addressing method is used to access external RAM and the upper half of the internal RAM.
The registers-pointers of 8-bit addresses can be the registers R0, R1 of the selected bank of working registers or the stack pointer SP, for 16-bit addressing, only the data pointer register DPTR is used.
Direct addressing.
With this method of addressing, the data is directly indicated in the command and is located in the second (or in the second and third) bytes of the command, i.e.
no memory addressing required.
For example, by the command MOV A, # 50, the number 50 is loaded into the accumulator A.
Indexed addressing.
This method is an indirect register addressing, in which the data byte address is determined as the sum of the contents of the base (DPTR or PC) and index (A) registers.
Way used only for access to program memory and only in read mode; it makes it easier to view tables hardwired into program memory.
Command structure.
The length of a command is one (49 commands), two (45 commands) or three (17 commands) bytes.
The first byte of the command always contains the opcode (OP), while the second and third bytes are the addresses of the operands or immediate data values.
Individual bits, tetrads, bytes and double-byte words can be used as operands.
There are 13 types of commands, which are shown in Table 7.3.5: 
● A, PC, SP, DPTR, Rn (n = 0, 7) - accumulator, instruction counter, stack pointer, data pointer register and current bank register;
● Rm (m = 0, 1) - register of the current bank used for indirect addressing;
● direct - 8-bit address of the directly addressed operand;
● bit - the address of the directly addressed bit;
● rel - relative address of the transition;
● addr11, addr16 - 11- and 16-bit absolute transition address;
● # data8, # data16 - direct data (operands) of 8- and 16-bit length;
● A10, A9, A0 - individual bits of the 11-bit address;
● (.) - the contents of the memory cell at the address specified in brackets;
● SB, MB - high and low bytes of the 16-bit operand.
General information about the command system.
The command system provides great possibilities for processing data in the form of bits, notebooks, bytes, double-byte words, as well as real-time control.
The ASM51 macro assembler language is used to describe the commands. The syntax for most commands consists of a mnemonic (abbreviation) of the operation to be performed, followed by the operands.
The operands are used to indicate different addressing methods and data types.
In particular, the abbreviation MOV has 18 different instructions designed to process three types of data (bits, bytes, addresses) in different address spaces.
The set of commands has 42 mnemonic designations of 111 types of commands to concretize 33 MK functions.
Of the 111 instructions, 64 are executed in one machine cycle, 45 in two cycles, and only two instructions (MUL - multiplication and DIV - division) are executed in 4 cycles. With a clock generator frequency of 12 MHz, the duration of a machine cycle (12 clock cycles) is 1 μs. By functional feature teams can be divided into five groups. Below is a description of the commands of each group, presented in the form of tables. For the compactness of the tables, let us single out a group of commands (Table 7.3.6), the execution of which influences(marked with +) on the state of flags status word register PSW. 
Data transfer commands
Transfer commands can be divided into separate subgroups.
Commands for transferring and exchanging data between cells of internal memory(Table 7.3.7).
Commands 1-16, which have the mnemonic MOV dest, src, are for forwarding byte or two bytes (command 16) of data from source src to destination dest, while:
● to indicate source(src) four addressing methods are used: register (commands 2-4, 6, 8), direct (commands 1, 7, 9, 11), indirect (commands 5, 10) and direct (commands 12-16);
● to indicate receiver(dest)
three methods are used: register (commands 1, 3 ... 5, 9, 12, 14, 16), direct (commands 2, 7, 8, 10, 13), indirect (commands 6, 11, 15). 
Teams 17-20 provide exchange information between two cells of the internal data memory (or two-way transfer).
When the XCH commands are executed, bytes are exchanged, A of the XCHD command is exchanged with the lower tetrads of byte operands.
One of the cells is always the accumulator A. As another cell, when exchanging bytes, one of the Rn registers of the current bank is used, A is also a directly or indirectly addressable cell of the internal memory; when exchanging tetrads - only an indirectly addressable cell of the internal memory.
Since in all MCUs the stack is located in the internal RAM, this subgroup includes commands(20, 21) stack access PUSH src, POP dest.
These commands use only direct addressing method, writing a byte onto the stack or recovering it from the stack.
It should be borne in mind that in those MCUs that do not have the upper 128 bytes in RAM, increasing the stack beyond 128 bytes leads to data loss.
Data transfer commands between internal and external data memory(Table 7.3.8).
These commands use only indirect addressing, while the one-byte address can be located in P0 or R1 of the current bank of registers, and the two-byte address can be located in the DPRT data pointer register.
In any access to external memory, battery A plays the role of receiver or source of operands in the internal memory. 
Data transfer instructions from program memory(Table 7.3.9).
These commands are for reading tables from program memory.
The MOVC A, @ A + DPTR instruction is used to refer to a table with the number of inputs from 0 to 255.
The number of the required table entry is loaded into the accumulator, and the DPTR register is set to the starting point of the table. A distinctive feature of the other command is that the program counter PC is used as a base pointer and the table is accessed from a subroutine. First, the number of the required entry point is loaded into the accumulator, then the subroutine is called with the command MOVC A, @ A + PC. The table can have 255 inputs with numbers from 1 to 255, since 0 is used for the address of the RET command of the subroutine exit. 
Arithmetic data processing commands. All arithmetic commands are performed on unsigned integers. Operations on two operands(Table 7.3.10). In operations additions ADD, carry-over addition ADDC and loan deduction SUBB: 
● the source of one 8-bit operand and the receiver of the result is the accumulator;
● the source of another operand is either one of the working registers Rn (n = 0-7) of the current bank, or directly direct
or indirectly @Rm (m = 0, 1) the addressable memory location of the RAM, or direct data #data.
Operations multiplication MUL and division DIVs are performed over the contents of registers A and B. When multiplying, the upper 8 bits of the result are written to register B, the lower 8 bits - to register A.
If the product is greater than 255, the OV overflow flag is set; carry flag C is always cleared. The DIV instruction divides the 8-bit operand of accumulator A by the 8-bit operand of register B.
During division, the quotient (most significant bits) is written into the register in A, the remainder (least significant bits) - in B. The carry flags C and overflow OV are cleared.
An attempt to divide by 0 sets the OV overflow flag. The division operation is more commonly used for shifts and base conversions.
When a binary number is divided by 2 N, it is shifted by N bits to the left.
Extra bits are transferred to register B.
Operations on single-byte operands(Table 7.3.11).
The DA command is used to perform BCD operations. INC, DEC commands allow respectively increasing or decreasing the contents of the memory cell by one.
They apply to the contents of the accumulator A, one of the working registers Rn, or a memory cell addressed both directly and indirectly.
The increment operation also applies to the contents of the 16-bit DPTR pointer register. 
Boolean commands.
Double operations
(Table 7.3.12).
AML, ORL, XRL commands allow performing three two-place logical operations on 8-bit operands: ANL - logical multiplication (AND), ORL - logical addition (OR), XRL - exclusive OR (XOR).
Operations are performed on individual bits of the operands. The source of one of the operands and at the same time the receiver of the result is either the accumulator (A) or a directly addressable memory cell (direct).
For the source of another operand, a register, direct, indirect or direct addressing method is used. 
Single operations
(Table 7.3.13).
The group also includes a number of single operations on the contents of accumulator A: clear (CLR), logical complement or inversion (CPL), cyclic and extended cyclic shifts by 1 bit to the right (RL, RLC) and left (RR, RRC), exchange tetrads or cyclic shift of a byte by 4 bits (SWAP), A is also an empty operation (NOP), as a result of which the state of all MK registers (except for the program counter) remains unchanged. 
Control transfer commands
Unconditional Jump Commands
(Table 7.3.14).
Commands 1-3 differ only in the format of the destination address.
The LJMP (L - Long) command performs a "long" unconditional jump to the specified addr16 address, loading the PC counter with the second and third command bytes.
The command provides a jump to any point in the 64K byte address space.
The AJMP (A - Absolute) command provides an "absolute" jump to an address within a 2K byte page, the starting address of which is set by the five most significant bits of the PC program counter (at first, the PC content is increased by 2).
The SJMP (S - Short) command allows a “short” unconditional jump to the address, which is calculated by adding the signed offset rel in the second command byte with the content of the PC counter, previously increased by 2.
The jump address is within -128 + 127 bytes relative to the command address.
To jump to any other point in the 64-kilobyte address space, command 4 with an indirect @ A + DPTR address can also be used.
In this case, the content of A is interpreted as unsigned integer. 
Null operation (NOP), as a result of which the state of all microprocessor registers (except for the program counter) remains unchanged.
Conditional branch commands
(Table 7.3.15).
With the help of the JZ and JNZ commands, a jump is performed if the contents of the accumulator are respectively equal or not equal to zero.
The jump address is calculated by adding the relative sign offset rel to the contents of the PC command counter after adding 2 (command length in bytes) to it.
The contents of the battery remain unchanged.
Commands do not affect flags. 
Commands CJNE (3-6) are used to implement a conditional jump based on the result of comparing two 8-bit operands, the location of which is indicated in the commands.
If their values are not equal, a branch is made.
The jump address is calculated by adding the offset rel with the content of the PC counter, previously increased by 3.
Otherwise, the next command is executed.
The Algorithm column shows the effect of the values of the compared 8-bit operands on the carry flag C.
DJNZ (7) commands are designed to organize program loops.
Register Rn or direct (direct) address is a counter of loop repetitions, A offset rel (in the second and third command bytes) is the relative address of the jump to the beginning of the loop.
When the commands are executed, the contents of the counter are decremented by one and checked for zero.
If the content of the counter is not equal to zero, the transition to the beginning of the cycle is performed.
Otherwise, the following command is executed.
The jump address is calculated by adding the offset to the counter content, previously increased by the length of the command (by 2 or 3).
Command flags are not affected.
Commands for calling subroutines and returning from programs
(Table 7.3.16).
The LCALL "long call" and ACALL "absolute call" commands unconditionally call the subroutine located at the specified address.
The difference between these instructions and the unconditional jump instructions discussed above is that they store the return address (the contents of the counter) to the main program on the stack.
The return command from the RET subroutine restores the value of the contents of the program counter from the stack, and the RETI command also enables interrupts of the service level. 
Relative addressing is widely used in control transfer commands, which supports relocatable program modules.
An 8-bit signed offset rel acts as a relative address, which provides for branching from the current position of the PC counter in both directions by ± 127 bytes.
To jump to any other point in the 64K-byte address space, either the direct addr16 address or the indirect @ A + DPTR address can be used.
In the latter case, the content of A is interpreted as unsigned integer.
A variant of the short direct addressing addr11 within a 2K-byte current page was introduced for compatibility with the MK48 architecture.
All these types of addressing can only be applied to the branch operation, and for the call operation only direct addr16 and internal addr11 addressing methods are allowed.
In all conditional operations, only relative addressing can be used.
When the MK51 recognizes an interrupt request, it generates one of the LCALL addr16 instructions, which automatically ensures that the return address is stored on the stack.
However, unlike MK48, MK51 does not have automatically saved status information.
In this case, the interrupt logic stops responding to requests of the level that was accepted for service.
To lower the interrupt level, the command to return from the RETI interrupt is used, which, in addition to the operation equivalent to RET, includes the operation of enabling the interrupt of this level.
Operations JZ, JNZ also belong to the standard conditional operations MK51.
However, there is a new operation "Compare and Go" CJNE.
For this command, the operand is first compared according to the rules of subtraction of integers with a constant, and in accordance with the result of the comparison, the CY flag is set. Then, in case of a mismatch with a constant, branching is performed. By comparing an accumulator, register or memory cell with a sequence of constants, we get a convenient way to check for coincidences, for example, in order to identify special cases.
In fact, the CJNE command is a member of the high-level language operator, type CASE.
The DJNZ team was further developed.
Now the programmer as a counter can use not only one of the working registers Rn, but also any DSEG memory cell.
Bit operations commands.
The group consists of 12 commands that allow you to perform operations on one or two bits (reset, set, bit inversion, A also logical AND and OR), and 5 commands designed to implement conditional jumps (Table 7.3.17). 
The instructions provide direct addressing of 128 bits located in six to eleven cells of the internal RAM with addresses 20h.
2Fh (Table 7.3.3), and 128 bits located in special-purpose registers whose addresses are multiples of eight (highlighted in Table 7.3.4 in bold).
When performing operations on two one-bit operands, the flip-flop of the PSW register, which stores the carry flag C (Table 7.1.2), is used as a logical accumulator.
The MOV (1,2) instructions perform shipment bit from one directly addressable bit cell of internal RAM to flip-flop C or vice versa.
Commands CRL (3, 4), SETB (5, 6) respectively dump to zero or establish in one carry flag C or the specified bit.
With the help of the CPL, ANL, ORL (7-12) commands, the logical operations of inversion, addition and multiplication are performed.
The group also includes commands (13-17) for implementing conditional branch operations with a relative 8-bit offset rel.
Transitions can be implemented both when the bit or the carry flag is set (commands 13, 16), and when it is cleared (commands 14, 17).
The JBC command, in addition to moving to the calculated address, when the condition (bit) = 1 is met, resets this bit to zero.
When executing conditional branch commands, the branch address is calculated after adding numbers 3 or 2 to the counter (reflecting the number of bytes in the command).
Intel is the ancestor of the architecture of the MCS-51 family, which got its name from the first representative of this family - the 8051 microcontroller, released in 1980 based on n-MOS technology. A successful set of peripheral devices, flexible choice of external or internal program memory and reasonable price ensured this microcontroller success in the market. From the point of view of technology, the 8051 microcontroller was a very complex product for its time - 128 thousand transistors were used in the crystal, which was 4 times more than the number of transistors in the 16-bit 8086 microprocessor. This microcontroller remains the core of the MCS-51 family to this day.
The main elements of the basic architecture of the family (architecture of the 8051 microcontroller) are:
8-bit ALU;
4 banks of registers, 8 in each;
Internal (resident) program memory 4 Kbytes, having the ROM or EPROM type (8751);
Internal (resident) data memory 128 bytes;
21 register of special functions;
Boolean processor;
Two 16-bit Timers / Counters;
Serial port controller (UART);
Interrupt controller with two priority levels;
Four 8-bit I / O ports, two of which are used as an address / data bus for accessing external program and data memory;
Built-in clock generator.
Then the 8052 microcontroller was released, which was distinguished by an increased amount of resident program and data memory, introduced by a third timer and, accordingly, an expanded interrupt controller.
The next fundamental step in the development of MCS-51 was the transfer of manufacturing technology to CMOS (modification 8xC51). This made it possible to implement the Idl (idle) and Power Down (reduced consumption) modes, which ensure a sharp decrease in the power consumption of the crystal and opened the way for the use of the microcontroller in volatile applications, for example, in stand-alone battery-powered devices.
And the last important stage in the development of MK 8051 by Intel was the release of microcontrollers 8xC51FA / FB / FC and 8xC51RA / RB / RC, which for short are often referred to as 8xC51Fx and 8xC51Rx. The main distinguishing feature of this group of crystals is that they have a dedicated timer / counter (PCA). In addition, the 8xC51Rx microcontrollers additionally contain a watchdog timer (WDT). Let's take a closer look at the architecture and functionality of the PCA.
The PCA includes:
16-bit timer / counter;
Five 16-bit sampling and comparison modules, each of which is connected to its own line of the I / O port of the microcontroller.
The timer / counter serves all five sample and compare modules, which can be programmed to perform one of the following functions:
16-bit sampling of the timer value on the positive edge of the external signal;
16-bit sampling of the timer value on the negative edge of the external signal;
16-bit sampling of the timer value on any edge of the external signal;
16-bit programmable timer;
16-bit high-speed output device;
8-bit PWM.
All of the above functions are performed in the PCA at the hardware level and do not load the central processor. This allows you to increase the overall throughput, improve the accuracy of measurements and signal processing, and reduce the response time of the microcontroller to external events, which is especially important for real-time systems. The PCA implemented in 8xC51Fx (8xC51Rx) turned out to be so
|
Designation |
Max. frequency (MHz) |
ROM / EPROM (byte) |
counters | ||
It is fortunate that the architecture of these microcontrollers has become an industrial standard, and the PCA itself has been repeatedly reproduced in various modifications of the MK 8051.
Some characteristics of a number of MCS-51 microcontrollers manufactured by Intel are shown in Table 1.1.
The initial bottlenecks of the MCS-51 architecture were the 8-bit battery-based ALU and relatively slow command execution (the fastest commands require 12 pe-
Table 1.1
|
input / output |
ADC, inputs x bits |
periphery, peculiarities |
U pit. (V) |
||
|
Low voltage option | |||||
|
4 levels IRQ, clock out | |||||
|
4 levels IRQ, clock out | |||||
|
Low voltage version 8xC51Fx | |||||
|
4 levels IRQ, clock out | |||||
|
4 levels IRQ, clock out | |||||
|
4 levels IRQ, clock out | |||||
period clock frequency (clock frequency MK)). This limited the use of microcontrollers of the family in applications requiring increased performance and complex calculations (16- and 32-bit). An urgent issue was the fundamental modernization of the MCS-51 architecture. The problem of modernization was complicated by the fact that by the beginning of the 90s a lot of developments in the field of software and hardware of the MCS-51 family had already been created, in connection with which one of the main tasks of designing a new architecture was the implementation of hardware and software compatibility with developments based on MCS -51.
To solve this problem, a joint group of specialists from Intel and Philips was created, but later the paths of these two companies went their separate ways. As a result, in 1995 two significantly different families appeared: MCS-251/151 for Intel and MCS-51XA for Philips (see subsection 1.2).
Main characteristics of MCS-251 architecture:
24-bit linear address space for addressing up to 16 MB of memory;
A register architecture that allows registers to be accessed as bytes, words, and double words;
Page addressing mode to speed up the retrieval of instructions from external program memory;
Queue of instructions;
Extended instruction set including 16-bit arithmetic and logical operations;
Extended address space of the stack (up to 64 KB);
Execution of the fastest command in 2 clock cycles.
The MCS-251 instruction set contains two instruction sets - the first set is a copy of the MCS-51 instruction set, and the second consists of extended instructions that take advantage of the MCS-251 architecture. Before using the microcontroller, it must be configured, i.e. with the help of the programmer, "burn" the configuration bits that determine which of the instruction sets will become active after power-up. If you install the first set of instructions, then in this case MCS-251 family will be compatible with MCS-51 at the binary code level. This mode is called Binary Mode. If you initially install a set of extended instructions (Source Mode), then the programs written for MCS-51 will require recompilation on cross-means for MCS-251. Source Mode allows you to make the most of the MCS-251 architecture and achieve the highest performance.
For users oriented to the use of MCS-251 microcontrollers as a mechanical replacement for MCS-51, Intel produces MCS-151 microcontrollers, already programmed in the Binary Mode state.
Some characteristics of a number of MCS-251/151 microcontrollers are shown in Table 1.1.
Currently, Intel, aiming at the Pentium-processor market, is phasing out production of MCS-51 crystals. In general, for a particular developer, this may go unnoticed, unless he uses microcontrollers 8xC51GB and 80C152Jx, which do not have their exact counterparts among products of other companies. As for all other microcontrollers of the MCS-51 family, all of them have been replicated many times by other companies.
The interrupt system status is polled at the end of each machine cycle in the S5P2 phase, with the exception of RETI commands and any commands referring to the IE and IP registers. From the moment of fixing the interrupt request to servicing the interrupt, it takes from 38 to 86 periods of the fOSC frequency, depending on the phase of the request and the number of machine cycles of the command during the execution of which the request was received.
When the interrupt is implemented in hardware, the LCALL addr16 instruction is executed, which ensures storing in the stack the current state of the program counter (storing the return address), and moving to the starting address addr16 of the corresponding service procedure. Each interrupt request source has its own
start address (interrupt vector): |
||||
External interrupt INT0. |
||||
Interrupt timer / counter TC0. |
||||
External interrupt INT1. |
||||
Interrupt timer / counter TC1. |
||||
Serial port interrupt. |
||||
2.7. Addressing Methods and Command System of the MCS-51 Family
The MCS-51 family command system is focused on organizing flexible data input-output through universal ports P0 ... P3 and primary information processing. Special attention is paid to operations with bits and transfer of control by their value. Instructions performing such operations constitute a large group and together with the corresponding hardware form the so-called "Boolean processor" in the MCS-51 architecture.
The instruction set provides the programmer with the ability to use most operations with a full set of addressing methods and software-available hardware resources.
2.7.1. Addressing methods
Each instruction tells the processor the operation to perform and the methods of accessing the operands. The command code has several fields that have a specific functional purpose. The most important fields of any command are the operation code (CPC), which determines the action of the command, and the address part. The fields of the address part contain information about the addresses of the operands and the result of the operation, and in some cases information about the address of the next command.
If the address indicates the number of the memory cell in which the operand is located or where it is entered, then it is called a direct address.
Addressing methods are a collection of mechanisms for accessing operands. Some of them are simple, lead to a compact instruction format and fast access to the operand, but have a limited amount of available resources. Others allow you to operate with all the resources available in the system, but the command turns out to be long, on its
input and execution is time consuming. The set of addressing methods in each instruction set is a compromise combination of known addressing mechanisms chosen by the architects based on the set of tasks to be solved.
The following are the main addressing methods used in the MCS-51 family commands.
Implicit addressing... The command does not contain explicit instructions about the address of the operand participating in the operation or the address at which the result of the operation is placed, but this address is implied. In commands, the accumulator is most often implicitly addressed as the receiver of the result of an operation. For example, the result of adding the contents of the accumulator (A) and the register R1 of the current databank with the ADD A, R1 command is written to the implicitly addressable accumulator. The entire specified command occupies one byte in memory, while the address of only the accumulator (8Eh of the SFR area) contains one byte.
Direct addressing... The command address field contains
The address is not the address of the operand, but the operand itself. Direct addressing is indicated by the special character # in front of the number. For example, with the MOV A, # 15h command, the hexadecimal number 15 (the second byte of the command) is loaded into the accumulator. In the command system, direct addressing is designated as #data, where data is a number
(data = 00h ... FFh).
Direct addressing... The command address field indicates the direct address of the data memory cell in which the operand is located or where it is written. For example, with the MOV A, 15h command, the contents of the DSEG cell with the address 15h are loaded into the accumulator. The memory cell is directly addressable, while the accumulator is implicit. Depending on the location of the addressed operand, direct addressing is subdivided into direct register and absolute.
Direct register addressing... The command address field contains the direct address of the register of the current register bank. There are eight registers in each bank, and a three-bit forward address is required to address them. In the mnemonics of commands, the addressable register is designated Rn, where n = 0 ... 7. All command fields fit in one byte. This is called short addressing. For example, MOV R4, R1.
Direct absolute addressing allows you to refer to any DSEG cell and SFR area. The direct address in this case is one byte, and the command is two bytes. In the command system, the direct address byte is designated by the word direct (direct = 00h… FFh). For example, the instruction MOV 80h, R2 (or MOV P0, R2) loads the contents of register R2 of the current data bank into port P0 (location 80h of the SFR area). If both operands are directly addressed, the instruction becomes three-byte (eg MOV 80h, 15h).
Indirect addressing... The address field contains the address of the memory cell in which the direct address of the operand is located. In the command system, the special character @ indicates indirect addressing. Property
the registers R0 and R1 (@Ri, i = 0,1) of each register bank possess the direct address. For example, if the contents of register R1 of the current bank of registers is 15h, then the MOV A, @ R1 instruction will perform the same action as the above instruction MOV A, 15h - it will load the contents of the DSEG memory cell with address 15h into the accumulator. However, the MOV A, @ R1 instruction is single-byte, but most importantly, it is possible to programmatically change the address by changing the contents of the R1 register.
Relative addressing... With relative addressing, the direct address is formed by adding the base address with the command address field. The content of the program counter is used as the base address, and the command address field is an eight-bit offset rel (relative). The rel number is interpreted by the command as a signed integer, represented in's two's complement. The range of its presentation is (-128 ... + 127). When determining the rel number, keep in mind that the program counter points to the next command to be executed. Relative addressing is widely used in control transfer commands, which allows you to create relocatable program modules. Control transfer commands with relative addressing allow organizing branching relative to the current position of the PC program counter in both directions by (-128 ... + 127) bytes.
In assembly language programs, you can specify the label to jump to in the offset field. As a result of translation, the assembler will calculate the offset value if it does not exceed (-128 ... + 127). Otherwise, an error message will be displayed.
Basic addressing represents a kind of relative addressing. The direct address in this case is formed by adding the address specified in the command with the contents of the base register, which stores the base address. The function of the basic register in the MCS-51 family is the DPTR data pointer register or the PC program counter. This type of addressing is especially useful when processing tables and data arrays. In the MOVC A, @ A + DPTR and MOVC A, @ A + PC instructions, the 16-bit forward address is formed as the sum of the contents of DPTR and A or PC and A.
Page addressing... When paging is used, memory is split into a series of pages of equal length. The pages are addressed by a separate page register, and the memory cells within the page are addressed by the address contained in the command. The direct address is formed by concatenating (appending) the address of the pages and the address of the memory cell within the page. In the MOVX A, @ Ri instruction, port P2 (address high byte) performs the function of the page register, and the contents of the Ri register (address low byte) sets the address within the page. In this case, the memory is divided into 256 pages of 256 cells in each of them.
Stack addressing It is used in unaddressed commands and is a combination of auto-incremental and auto-decremental addressing methods, operating on the LIFO (L ast I nput - F irst O utput) principle - "last in - first out". The stack is located in DSEG and grows in the direction of increasing address. The address of the top of the stack is contained in the SP stack pointer. When a byte is written to the stack, the SP contents are incremented first, and then a write is made to this address. When reading a byte from the stack, it reads first at the address pointed to by SP, and then decrements SP. When using a stack, keep in mind that the depth of the stack (the maximum number of memory cells occupied by the stack) is not controlled by hardware. With an excessive increase in the stack, memory cells that are not intended for it can be occupied with the loss of information in them. The hardware stack is used to store the return address when servicing the interrupt.
2.7.2. MCS-51 family command set
The command system is presented in tables A2.1 ... A2.6 of Appendix 2. The tables indicate the name of the command, its mnemonic, the binary operation code, the influence of the command being executed on the flags C, OV, AC and P, the length of the command in bytes (B) and the execution time in machine cycles (C), as well as the content of the transformation performed by the instruction. A comma is used as a separator for address fields in commands. To improve readability, you can add spaces after the comma if the assembler being used supports them.
The whole set of commands can be divided into 5 groups: data transfer operations, arithmetic operations, logical operations, bit operations and control transfer operations.
Group of commands for data transfer operations(table A2.1) with-
holds MOV (data transfer between DSEG and RSEG), MOVC (between CSEG and A), MOVX (between XSEG and A), PUSH and POP stack access commands, and two exchange commands XCH and XCHD. All data transfer commands, in which the receiver is the battery, set the parity flag P of the battery contents, and direct address commands, in which the PSW register is the receiver, change all flags. The most capacious is the MOV instruction, which uses four addressing methods: register direct (A, Rn, DPTR), direct (direct), indirect (@Ri), direct (#data, # data16). The second operand of the instruction is the source, the first is the destination. There are three addressing methods (except for direct) to indicate the destination, and all four to indicate the source. The three-byte MOV direct, direct command transfers between any two memory locations (DSEG and SFR), including RSEG. For exchange with RSEG, special two- and one-byte formats are provided:
The special MOV DPTR instruction, # data16, loads the 16-bit DPTR pointer with data16.
The MOVC instruction allows you to read information from the CSEG program memory not into the command register of the control device, but into the battery of the operating device. The command uses two addressing methods: based on DPTR and relative to PC. In both cases, the unsigned integer offset (index) is stored in the accumulator. The battery also serves as the receiver of the result. The command allows you to perform fast transcoding across tables.
External memory is accessed using the MOVX instruction. The exchange is performed by bytes between the battery and the external XSEG. The XSEG cell can be addressed in two ways: indirectly through the 16-bit DPTR pointer and paged indirectly through the 8-bit Ri, i = 0,1. In the latter case, the register of pages is the register P2.
Unaddressed PUSH and POP commands provide data transfer
between DSEG, RSEG and SFR.
The XCH exchange instruction provides a two-way exchange of bytes, and the XCHD instruction provides the least significant tetrads of byte operands.
Arithmetic command group(table A2.2) co-
holds instructions for addition ADD, addition with carry ADDC, subtraction with borrow SUBB, increment and decrement by one INC and DEC, packed format BCD addition decimal correction, MUL multiplication, and DIV division. Operations are performed on unsigned integers. In operations of addition and subtraction, the accumulator is the first operand and receiver of the result. Direct register, direct absolute, direct and indirect addressing are used to define the second operand. The INC and DEC operations apply to an accumulator, a directly addressable register, or a directly or indirectly addressable memory location. In addition, the INC operation applies to the contents of the 16-bit DPTR pointer register.
The unsigned integer multiplication and division operations involve the accumulator and register B. In multiplication, the 8-bit value of A is multiplied by the 8-bit value of B, and the 16-bit result is written to the BA pair. In this case, register B stores the upper part of the product. The OV flag is set if the product is greater than 255. When an 8-bit value A is divided by an 8-bit value B, the quotient is written to A, and the remainder is written to B. An attempt to divide by 0 sets the OV overflow flag.
The accumulator decimal correction command DA is placed after the add command. The terms must be represented in the BCD code. Correction is performed in a standard way.
Group of commands for logical operations(table A2.3 ) contains three typical operations: ANL - logical AND, ORL - logical OR, XRL - logical exclusive OR. The source of the first operand
either accumulator A or directly addressable memory cell serves. The second operand is specified by one of four basic addressing methods. The group also includes single operations over the contents of the accumulator: CLR - clear, CPL - inversion, and also RL, RLC, RR and RRC - operations of cyclic and extended shifts to the right and to the left. This also includes the operation of exchanging notebooks in the SWAP accumulator, which can be interpreted as a cyclic shift of a byte by four digits.
Bit Operations Command Group(table A2.6) contains co-
Commands SETB - setting a bit to 1, CLR - resetting a bit to 0, CPL - bit inversion, ANL and ORL - logical AND and logical OR of the contents of the C flag and a directly addressed bit, MOV - bit transfer.
V bit operations, the C flag acts as a boolean accumulator. The operands are the contents of the C flag or the directly addressable bit of the BSEG. ANL and ORL operations can use the content of a direct addressable bit (bit) or inversion of content (/ bit).
V this group also includes commands for conditional branching with relative 8-bit offset rel. A conditional jump can be performed with both set (JB command) and cleared (JNB command) bit. Of particular note is the JBC command, which, when the bit is set, implements branching and at the same time clears the bit to 0.
Control transfer command group(tables A2.4 and A2.5) with-
holds unconditional jump commands AJMP, LJMP, SJMP, JMP, conditional jump JZ, JNZ, CJNE, call ACALL, LCALL, return RET, RETI and modify with conditional jump DJNZ. An empty NOP command is also included.
V Relative addressing is widely used in control transfer commands, allowing you to create relocatable program modules. The relative address is 8-bit offset rel is a signed byte that provides a jump (–128 ... +127) bytes relative to the current PC position. Either the direct addr16 or the indirect @ A + DPTR address can be used to jump to any other point in the 64K address space. In the latter case, the content of A is interpreted as unsigned integer. A variant of the short direct addressing addr11 within the 2KB current page was introduced for compatibility with the MCS-48 family.
All of these types of addressing are used in jump instructions. In call commands, only direct addr16 and in-page addr11 addressing methods are used. All conditional commands use only relative addressing.
When the microcontroller recognizes the interrupt request, it generates the LCALL addr16 instruction, which automatically ensures that the return address is stored in the stack. Program status information (PSW register contents) is not automatically saved. Wherein
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