UDC 681.5, 681.325.5 (075.8)

BBK 32.973.202-018.2 i 73

Shcherbina A.N.Computing machines, systems and networks. Microcontrollers and microprocessors in control systems: cheb. allowance / A.N. Shcherbina, P.A. Nechaev- SPb .: From the Polytechnic. University, 2012.-226 p.

Corresponds to the content of the state educational standard for areas of training and specialties in the field of management in technical systems, electric power and electrical engineering and the content of the exemplary curriculum for the discipline "Computing machines, systems and networks".

The fundamental issues of the logical organization of microprocessor systems are considered on the example of the basic architecture of the MCS-51 microcontroller family from Intel. The technology of programming microcontrollers in Assembler and SI languages ​​is described.

It can be useful for students and teachers of higher technical institutions, specialists in the automation of technological processes and production equipment, as well as for design engineers of microprocessor systems.

It also complies with the content of the state educational standard of disciplines "Microcontrollers and microprocessors in control systems" and "Electronic devices of automation" bachelor's, engineering and master's training in the direction 140400 "Electrical power and electrical engineering".

Reprinted by the decision of the Editorial and Publishing Council

St. Petersburg State Polytechnic University.

© Shcherbina A. N., Nechaev P. A., 2012

© St. Petersburg State

Polytechnic University, 2012

ISBN 978-5-7422-3553-8

Introduction .. 7

Chapter 1. Architecture of the MCS51 family. ten

1.1 General characteristics 10

1.2 Block diagram 11

1.3 Pin assignment of the 8051 microcontroller 15

1.4 Memory organization 17

1.4.1 Program memory (ROM) 18

1.4.2 Data memory (RAM) 19

1.4.3 Registers of special functions. twenty

1.4.4 Flags Register (PSW) 23

1.5 Control and synchronization device 26

1.6 Arrangement of I / O Ports 27

1.6.1 General information. 27

1.6.2 Alternative functions. 27

1.7. Timers / Counters for 8051 microcontrollers.28

1.7.1. Timer-counters structure. 28

1.7.2 Modes of operation of timers-counters. thirty

1.8. Serial port 32

1.8.1. Serial port structure. 32

1.8.2. Transceiver control / status register SCON .. 34

1.8.3. Power control register PCON .. 36

1.9. Interrupt system 37

1.9.1. Interrupt system structure. 37

1.9.2 Execution of interrupt routines. 40

Chapter 2. Features of the 80C51GB microcontroller .. 42

2.1 Features 42

2.2 I / O Ports P0-P5 43

2.2.1 Functioning of the input-output ports. 43

2.2.2 Writing to Port .. 46

2.3 Features of the 8XC51GB interrupt system .. 49

Enable / disable interrupts. 50

Interrupt priority management. 51

External interrupts. 54

2.3. ADC Node 56

2.4. Hardware Watchdog 61

2.5. Clock Failure Detection 63

2.6. Matrix of programmable counters RSA 64

2.6.1. Structure of the PCA .. 64

2.6.2. PCA counter mode register (CMOD) 66

2.6.3. PCA counter control register (CON) 67

2.6.4. Compare / commit modules. 68

2.7. Extended Serial Port 76

2.8. Timers / Counters 79

Pinout of microcontrollers group 8XC51GB .. 86

Chapter 3. Programming MK 8051GB .. 89

3.1. Programming Model 89

3.2 Data Types 93

3.3 Methods of data addressing 93

3.4 Command System 95

3.4.1 General characteristics. 95

3.4.2 Command types. 96

3.4.3 Types of operands. 97

3.4.4 Commands for transferring microcontroller data. 98

3.4.5 Commands for arithmetic operations 8051.101

3.4.6 Commands of logical operations of microcontroller 8051.104

3.4.7 Commands for operations with bits of microcontroller 8051.106

3.5 Debugging Programs 111

Chapter 4. Programming language ASM-51. 112

4.2 Writing Program Text 113

4.3 The alphabet of the language. 114

4.4 Identifiers. 115

4.5 Numbers 117

4.6 Directives 118

4.7 Implementation of subroutines in ASM51 language 122

4.7.1 The structure of a subroutine-procedure in the ASM51 language. 122

4.7.2 Passing variable parameters to a subroutine. 123

4.7.3 Implementation of subroutine functions in ASM51 language. 123

4.7.4 Implementation of interrupt handling routines in ASM51 language. 124

4.8 Structured programming in assembly language. 125

4.9 Features of broadcasting multi-module programs. 126

4.10 Using segments 128

4.10.1 Splitting the MK memory into segments .. 128

4.10.2 Absolute memory segments. 129

4.10.2 Relocatable memory segments. 131

Chapter 5. Programming language С-51. 134

5.1 General characteristics of the language 134

5.3 Structure of the C-51 programs 136

5.3. Elements of the C-51 programming language 138

5.3.1. Symbols .. 138

5.3.2. Lexical units, separators and the use of spaces. 141

5.3.3 Identifiers .. 142

5.3.4 Keywords. 143

5.3.5 Constants .. 143

5.4. Expressions in Language Operators 146

programming C-51 146

5.5. Priorities for Operations 148

5.6. Operators of the C-51 programming language 149

5.6.1. Declaration operators. 150

5.6.2 Executable Operators .. 150

5.6.3 The assignment operator. 151

5.6.4 Conditional operator. 151

5.6.5 Structured operator (). 152

5.6.6 Loop operator for. 152

5.6.7 Operator of the loop with checking the condition up to the body of the while loop. 153

5.6.8 Operator of the loop with checking the condition after the body of the loop do while. 154

5.6.9 Operator break. 155

5.6.10 Operator continue. 155

5.6.11 The operator of choice switch. 155

5.6.12 Operator of unconditional branch goto. 157

5.6.13 Operator expression. 158

5.6.14 Operator of return from subroutine return. 158

5.6.15 Empty statement. 158

5.7. Declaring variables in the C-51 programming language. 159

5.7.1. Variable declaration. 159

5.7.3 Integer data types. 161

5.7.4 Floating point numbers. 162

5.7.5 Variables of enumeration type. 162

5.7.6. Declaring arrays in the C-51 programming language. 164

5.7.7. Structures .. 165

5.7.8. Combinations (mixtures) 166

5.8. Using Pointers in C-51 167

5.8.1. Declaration of pointers. 167

5.8.2. Untyped pointers. 168

5.8.3. Memory dependent pointers. 169

5.9. Declaring New Variable Types 169

5.10. Data initialization 170

5.11. Using subroutines in the C-51 programming language. 170

5.11.1. Defining subroutines. 171

5.11.2. Parameters of subroutines. 173

5.11.3. Pre-declaration of subroutines. 174

5.11.4 Calling subroutines .. 176

5.11.5 Recursive call of subroutines. 176

5.11.6 Interrupt handling routines. 177

5.11.7 Scopes of variables and subroutines. 178

5.12. Multimodal programs 179

Chapter 6. Preparing programs in the Keil μVision2 integrated development environment. 182

6.1 Creating a Project in ASM-51 Language 182

6.2 An example of creating a project in C language for a training controller in the Keil μVision2 integrated development environment 188

Chapter 7. Description of the training controller .. 199

7.1. Controller structure 199

7.2. Address space 200

7.2.1. Memory allocation. 200

7.2.2 External memory. 201

7.2.3. Internal data memory. 202

7.3. I / O Port Mapping 202

7.4. Serial port ……………………………… ... 203

7.5. Working with LCD 205

7.6. Controller panels ………………………………………………… 213

APPENDIX P2 STRUCTURE OF THE LABORATORY REPORT …… ..217

Appendix A3 Codes of machine instructions. 217

References ... 224

Introduction

In the development of specialties related to the automation of technological processes and production, the study of microcontrollers is one of the important sections.

There is a continuous development and the emergence of more and more 16- and 32-bit microcontrollers and microprocessors in the world, but the largest share of the world microprocessor market still belongs to 8-bit devices. According to all forecasts of analytical companies for the near future, the leading position of 8-bit microcontrollers in the world market will remain.

Currently, among all 8-bit microcontrollers, the MCS-51 family is the undoubted leader in terms of the number of varieties and the number of companies producing its modifications. It got its name from the first representative of this family - the 8051 microcontroller. A successful set of peripheral devices, flexible choice of external or internal program memory and reasonable price ensured this microcontroller success in the market.

Advantages of the MCS-51 family:

· Architecture, which is a de facto standard;

· The extraordinary breadth of the family and the variety of possibilities;

· Availability of high-performance and extended versions of processors;

· A significant number of freely available software and hardware developments;

· Ease of hardware programming, including in-circuit programming;

· Low cost and availability of basic chips;

Availability of specialized versions of controllers for special conditions of use

· Availability of versions of controllers with a reduced level of electromagnetic interference;

· Widely known among the developers of the older generation, both in the world and in the CIS countries;

· Support of architecture by the world's leading educational institutions.

And finally, the main advantage: having mastered the basic chip of the family, you can easily start working with such computing "monsters" as microcontrollers Cygnal, Dallas Semiconductor, Analog Devices, Texas Instruments.

The MCS-51 family includes a number of microcircuits from the simplest microcontrollers to the most complex ones. Today there are more than 200 modifications of the 8051 family of microcontrollers, produced by almost 20 companies. Every year, new variants of representatives of this family appear.

The main directions of development are:

· Increase in performance (increase in clock frequency and redesign of the architecture);

· Reduction of supply voltage and power consumption;

· An increase in the amount of RAM and FLASH memory on a chip with the possibility of in-circuit programming;

· Introduction of complex devices such as drive control systems, CAN and USB interfaces, etc. into the microcontroller periphery.

Microcontrollers of the MCS-51 family allow you to perform both control tasks for various devices and implement individual analog circuit nodes. All microcircuits of this family work with the same instruction set. Most of them are made in identical cases with the same pinout (numbering of the legs for the case). This allows the use of microcircuits from different manufacturers for the developed device without altering the circuit diagram of the device and program.

The main manufacturers of varieties of the 51st family in the world are Philips, Siemens, Intel, Atmel, Dallas, Temic, Oki, AMD, MHS, Gold Star, Winbond, Silicon Systems and a number of others.

The characteristics of analogs of microcontrollers of the MCS-51 family (Intel 8XC51FA, 8XC51GB, 80C152) with extended capabilities are shown in Table. IN 1.

Table B.1

	RAM	ROM	PCA	ADC	WDT	T / C	Afterbirth. Channels	Peculiarities
Atmel: AT89C2051
	-	-	-	-		UART	Flash 2 Kb
AT89C4051		-	-	-	-		UART	Flash 4Kb
AT89S4D12		128K	-	-	-		UART, SPI	Flash 4Kb
DALLAS Semiconductor: DS5000FP
	-	-	-	+		UART	Bootstrap loader
DS5001FP		-	-	-	+		UART	Bootstrap loader
DS8xC520		16K	-	-	+		2xUART	2 DPTR
SIEMENS: C505C
	16K	-	+	+		UART, CAN	8 DPTR
C515C		64K	-	+	+		UART + SSC + CAN	4 PWM, 8 DPTR
Philips: * 89C51RA +
	-	+	-	+		UART	2 DPTR, 4 lv. interrupt, clock out, Flash 8K
P51XAG1x		8K	-	-	+		2 UART
Intel: 8xC51RA
	8K	-	+	+		UART	4 levels IRQ, clock out
8XC196KC	64K	16K	-	+	-		UART	3 PWM
80C196KB	64K	8K	-	+	-		UART	PWM

Chapter 1. Architecture of MCS51 Family

MCS-51 8-bit single-chip microcontrollers have become very popular among microprocessor control system designers due to their well-designed architecture. The architecture of a microcontroller is a collection of internal and external software-accessible hardware resources and a set of instructions. The architecture of the MCS-51 family is largely predetermined by its purpose - the construction of compact and cheap digital devices. Microcontrollers that perform all the functions of a microcomputer using a single microcircuit are called single-chip computers (OEVM).

Intel has released about 50 models based on the operating core of the Intel 8051 microcontroller. At the same time, many other firms, such as Atmel, Philips, began producing their own microcontrollers developed in the MCS-51 standard.

General characteristics

The main characteristics of the family:

· 8-bit central processing unit (CPU), focused on controlling executive devices;

· The CPU has a built-in circuit for 8-bit hardware multiplication and division of numbers;

· The presence in the instruction set of a large number of operations for working with directly addressable bits makes it possible to talk about a processor for working with bit data (boolean processor);

· Internal (located on the chip) program memory of the masked or reprogrammed type, which for various crystals has a volume of 4 to 32 Kb, in some versions it is absent;

· Not less than 128 bytes resident data RAM, which is used for organization, register banks, stack and storage of user data;

· At least 32 bidirectional interface lines (ports), individually configured to input or output information;

· Two 16-bit multi-mode counters / timers used to count external events, organize time delays and clock the communication port;

· Bi-directional duplex asynchronous transceiver (UART), designed to organize communication channels between the microcontroller and external devices with a wide range of data transfer rates. There are tools for hardware and software integration of microcontrollers into a connected system;

· Two-level priority interrupt system supporting at least 5 vectors of interrupts from 4 internal and 2 external sources of events;

· Built-in clock generator.

Structural scheme

The block diagram of the controller is shown in Figure 1.1 and consists of the following main functional units: control unit, arithmetic logic unit, timer / counter unit, serial interface and interrupt unit, program counter, data memory and program memory. Bidirectional exchange is carried out using an internal 8-bit data highway. Almost all representatives of the MCS-51 family are built according to this scheme. Different microcircuits of this family differ only in special-purpose registers (including the number of ports).

Timing and Control Unit- designed to generate synchronizing and control signals that ensure the coordination of the joint operation of the OEVM units in all permissible modes of its operation. The control unit includes:

device for forming time intervals;

I / O logic;

register of commands;

electricity consumption control register;

decoder of commands, computer control logic.

Rice. 1.1. Block diagram of the I8051 controller.

Time slot shaping device is intended for the formation and issuance of internal sync signals of phases, clocks and cycles. The number of machine cycles determines the duration of the instruction execution. Almost all OEVM commands are executed in one or two machine cycles, except for multiplication and division commands, the duration of which is four machine cycles. Let us designate the frequency of the master oscillator by F g. The duration of the machine cycle is 12 / F g or 12 periods of the signal of the master oscillator. The input-output logic is designed to receive and issue signals that provide information exchange with external devices through the P0-P3 input / output ports.

Command register is intended for recording and storing the 8-bit operation code of the command being executed. The operation code, with the help of a command decoder and computer control logic, is converted into a command execution microprogram.

Consumption Control Register (PCON) allows you to stop the microcontroller to reduce power consumption and reduce the level of noise from the microcontroller. Further reduction of power consumption and noise reduction can be achieved by stopping the master oscillator of the microcontroller. This can be achieved by flipping a bit in the consumption control register PCON. For n-MOS (1816 series or foreign ICs with no "c" in the middle), the PCON Consumption Control Register contains only one bit to control the SMOD serial port baud rate, and there are no power control bits.

Arithmetic Logic Unit (ALU) is a parallel eight-bit device that performs arithmetic and logical operations. ALU consists of:

accumulator registers, holding registers TMP1 and TMP2;

ROM of constants;

adder;

additional register (register B);

battery (ACC);

program status register (PSW).

Register accumulator and holding registers- eight-bit registers intended for receiving and storing operands for the duration of operations on them. These registers are not programmatically accessible.

ROM constants provides the generation of a correction code for binary-decimal data representation, a mask code for bit operations and a constant code.

Parallel eight-bit adder is a combination-type circuit with sequential carry, designed to perform arithmetic operations of addition, subtraction and logical operations of addition, multiplication, unequal and identical.

Register B- an eight-bit register used during multiplication and division operations. For other instructions, it can be viewed as an additional super-operative register.

Battery- an eight-bit register designed to receive and store the result obtained when performing arithmetic-logical operations or shift operations

Serial interface and interrupt block (PIP) is intended for the organization of input-output of sequential streams of information and the organization of a program interruption system. The block includes:

PIP buffer;

control logic;

control register;

transmitter buffer;

receiver buffer;

serial port transceiver;

interrupt priority register;

interrupt enable register;

interrupt flag processing logic and vector generation circuit.

Program Counter is designed to form the current 16-bit address of the internal program memory and the 8/16-bit address of the external program memory. The instruction counter includes a 16-bit PC buffer, a PC register, and an increment circuit (increasing the content by 1).

Data memory (RAM) is intended for temporary storage of information used in the process of program execution.

Ports P0, P1, P2, P3 are quasi-bidirectional input-output ports and are designed to ensure the exchange of information between the computer and external devices, forming 32 input-output lines.

Program Status Register (PSW) intended for storing information about the state of the ALU during program execution.

Program memory (EPROM) is intended for storing programs and is a read-only memory (ROM). Different microcircuits use mask, UV-erasable or FLASH ROM.

Data Pointer Register (DPTR) is designed to store a 16 - bit address of external data memory.

Stack Pointer (SP) is an eight-bit register designed to organize a special area of ​​data memory (stack), in which any memory cell can be temporarily stored.

1.3 Pin assignment of the microcontroller 8051(fig. 1.2)

· U ss - potential of the common wire ("ground");

· U cc - main supply voltage +5 V;

· X1, X2 - leads for connecting a quartz resonator;

RST - microcontroller general reset input;

· PSEN - permission of the external program memory, issued only when accessing the external ROM;

· ALE - strobe of the external memory address;

· ЕА - disable internal program memory; level 0 at this input forces the microcontroller to execute the program only from the external ROM; ignoring the internal (if the latter is available);

Rice. 1.2. Pin assignment 8051.

· P1 - eight-bit quasi-bidirectional input / output port, each bit of the port can be programmed both for input and output of information, regardless of the state of other bits;

· P2 - an eight-bit quasi-bidirectional port, similar to P1, the pins of this port are used to issue address information when accessing external program or data memory (if the latter is 16-bit addressing). In addition, the pins of the port are used during programming to enter the high-order bits of the address into the microcontroller;

РЗ - an eight-bit quasi-bidirectional port, similar to P1, the pins of this port can perform a number of alternative functions that are used during the operation of timers, a serial input-output port, an interrupt controller, and external program and data memory;

· P0 - multiplexed eight-bit bidirectional information input-output port, through this port at different times the low byte of the address and data are output.

Organization of memory

The entire MCS-51 series has a Harvard architecture, that is, separate address spaces for program and data memory. The memory structure is shown in Fig. 1.3.

The amount of internal (resident) program memory (ROM, EPROM or OTP ROM) located on the chip, depending on the type of microcircuit, can be 0 (ROMless), 4K (base crystal), 8K, 16K or 32K. If necessary, the user can expand the program memory by installing an external ROM. Access to the internal or external ROM is determined by the value of the signal at the EA pin (External Access):

EA = V cc (supply voltage) - access to the internal ROM;

EA = V ss (ground potential) - access to external ROM.

For crystals without ROM (ROMless), the EA pin must be permanently connected to V ss.

Rice. 1.3. Memory organization of the MCS-51 family

External ROM read strobe - (Program Store Enable) is generated when accessing the external program memory and is inactive during access to the ROM located on the chip. The area of ​​the lower addresses of the program memory is used by the interrupt system. The architecture of the basic 8051 chip provides support for five interrupt sources:

· Two external interrupts;

· Two interrupts from timers;

· Interrupts from the serial port.

In fig. 1.4 shows a map of the lower area of ​​program memory.

Rice. 1.4. Lower program memory map

Program memory (ROM)

In microcontrollers of the 8051 family, the program memory and data memory are independent and independent devices, addressed by various commands and control signals.

The built-in program memory located on the chip of the 8051 microcontroller is 4 KB (in the family up to 32). When accessing external program memory, all microcontrollers of the 8051 family always use a 16-bit address, which provides them with access to 64 KB of ROM. The microcontroller accesses program memory when reading the opcode and operands (using the PC instruction counter), as well as when executing instructions to copy a byte from program memory to the battery. When executing the data copying instructions, the addressing of the program memory cell from which the data will be read can be carried out using both the PC counter and the special two-byte DPTR data pointer register.

Data memory (RAM)

The on-chip data memory is 128 bytes. The external data memory can be up to 64KB. The first 32 bytes are organized into four banks of general-purpose registers, designated respectively bank 0 - bank 3. Each of them consists of eight registers R0 – R7. At any time, the program is available, with register addressing, only one bank of registers, the number of which is contained in the third and fourth bits of the status word of the PSW program.

8051 microcontroller memory bit area addresses

Table 1.1

Byte address (Hex)	Bit addresses by bit
D7	D6	D5	D4	D3	D2	D1	D0
2F	7F	7E	7D	7C	7B	7A
2E
2D	6F	6E	6D	6C	6B	6A
2C
2B	5F	5E	5D	5C	5B	5A
2A
	4F	4E	4D	4C	4B	4A
	3F	3E	3D	3C	3B	3A
	2F	2E	2D	2C	2B	2A
	1F	1E	1D	1C	1B	1A
	0F	0E	0D	0C	0B	0A
20h

The remaining address space can be configured by the developer at his discretion: it can accommodate the stack, system and user data areas. Data memory cells can be accessed in two ways. The first way is direct addressing of a memory cell. In this case, the cell address is the operand of the corresponding instruction. The second method is indirect addressing using the R0 or R1 pointer registers: before executing the corresponding command, the address of the cell to be addressed must be entered into one of them.

To access external data memory, only indirect addressing is used using the R0 and R1 registers or using the 16-bit DPTR pointer register.

Part of the data memory is a bit area, in which it is possible, with the help of special bit instructions, to address each bit of memory cells. The address of directly addressable bits can also be written as (ByteAddress). (Bit). The correspondence of these two addressing methods can be determined from Table. 1.1.

At present, various firms produce many modifications and analogues of this family, both by Intel and other manufacturers, the clock frequency and memory capacity have grown tenfold and continue to increase. The set of modules built into the LSI is also being supplemented; a large number of modern models are equipped with a resident high-speed ADC, which has up to 12, and now there may be more digits. But at the heart of the MCS51 family are BIS 8051, 80C51, 8751, 87C51, 8031, 80C31 from Intel, the first samples of which were released in 1980.

Microcontrollers of the MCS51 family are made using high-quality n-MOS technology (series 8XXX, analogue - series 1816 in Russia and Belarus) and k-MOS technology (series 8ХСХХ, analogue - series 1830). The second character following 8 means: 0 - no on-chip EPROM, 7 - 4K EPROM with UV erasure. The third symbol: 3 - ROM will be crystallized, 5 - if there is no EPROM, then a mask ROM will be on the chip.

And so 80S51 - LSI according to k-MOS technology with masked ROM on a chip, 8031 ​​- LSI n-MOS without program memory (ROM, EPROM) on a chip, 8751 - LSI n-MOS with resident (located on a chip) EPROM with ultraviolet erasure. We will further consider the LSI 8751, making, if necessary, reservations about the differences in other circuits, giving those parameters that were published for the first serial LSI. If necessary, you can find additional information about all modern modifications in the company manuals and technical documentation.

A. General characteristics and pin assignment

The MCS51 family is based on five modifications of MK (having identical basic characteristics), the main difference between which is the implementation of program memory and power consumption (see Table 3.1). The microcontoller is eight-bit, i.e. has commands for processing eight-bit words, has a Harvard architecture, the clock frequency of the basic samples of the family is 12 MHz.

Table 3.1.

Microcircuits	Internal program memory, bytes	Program memory type	Internal data memory, bytes	Clock frequency, MHz	Consumption current, mA

MK 8051 and 80C51 contain a mask-programmable ROM of program memory with a capacity of 4096 bytes during the manufacture of a crystal and are designed for use in mass production. MK 8751 contains an EPROM with a capacity of 4096 bytes with ultraviolet erasure and is convenient at the stage of system development when debugging programs, as well as when producing in small batches or when creating systems that require re-

periodic adjustment.

MK 8031 ​​and 80C31 do not contain built-in program memory. They, like the previously described modifications, can use up to 64 Kbytes of external program memory and can be effectively used in systems requiring a much larger volume (than 4 Kbytes on a chip) of program memory.

Each MC of the family contains resident data memory with a capacity of 128 bytes with the possibility of expanding the total amount of RAM data up to 64 Kbytes through the use of external IC RAM.

central eight-bit processor;

4 KB program memory (8751 and 87C51 only);

data memory of 128 bytes;

four eight-bit programmable I / O ports;

two 16-bit multi-mode timers / counters;

a system of auto-vector interrupts with five vectors and two software-controlled priority levels;

a serial interface including a universal duplex transceiver capable of operating in four modes;

clock generator.

The MK command system contains 111 basic commands with the format 1, 2, or 3 bytes. The microcontroller has:

32 general-purpose registers RON, organized as four banks of eight registers each with the names R0 ... R7, the choice of one or another bank is determined by the program by setting the corresponding bits in the PSW program status register;

128 software-controlled flags (bit processor, see below);

a set of registers of special functions that control MK elements. There are the following operating modes of the microcontroller:

1). General reset. 2). Normal functioning. 3). Low power mode and idle mode. 4). Resident EPROM programming mode, if any.

Here we will focus on the first two modes of operation, a detailed description of the composition and operation of the MC in all modes is given in Appendix A1.

RON and the bit processor zone are located in the address space of the resident RAM with addresses from 0 to 80h.

In the upper zone of addresses of resident random access memory there are registers of special functions (SFR, Special Function Registers). Their purpose is given in table. 3.2.

Table 3.2.

Designation	Name
	Battery
	Register B
	Program status register
	Stack pointer
	Data pointer. 2 bytes:
	Least significant byte
	High byte
	Interrupt Priority Register
	Interrupt enable register
	Timer / Counter Mode Register
	Timer / Counter Control Register
	Timer / Counter 0. High Byte
	Timer / Counter 0. Low Byte
	Timer / Counter 1. High Byte
	Timer / Counter 1. Low Byte
	Serial port control
	Serial port buffer
	Consumption management

* - registers, admitting bitwise addressing

Let's take a quick look at the functions of the SFR registers shown in Table 3.2.

Battery ACC - battery register. Commands designed to work

you with a battery, use the mnemonic "A", for example, MOV A, P2 ... The "ACC" mnemonic is used, for example, for bitwise battery addressing. So, the symbolic name of the fifth bit of the accumulator when using the assembler A5M51 will be as follows: ACC. 5. .

Register V ... Used during multiplication and division operations. For other instructions, register B can be considered as an additional super-operative register.

Register fortunes programs PSW contains information about the state of the program and is installed partially automatically based on the result of the operation performed, partially by the user. The designation and purpose of the register bits are given in tables 3.3 and 3.4, respectively.

Table 3.3.

Designation

Table 3.4.

	Designation			Bit assignment		Access to the bit
				Carry flag. Changes during the execution of a series of arithmetic and logical instructions.		Hardware or software
				Additional carry flag. Hardware set / cleared during addition or subtraction instructions to indicate carry or borrow in bit 3 when the least significant nibble of the result (D0-D3) is generated.		Hardware or software
				Flag 0. User-defined flag.		Programmatically
						Programmatically
				Work register bank pointer		Programmatically
			Bank 0 with addresses (00H - 07H) Bank 1 with addresses (08H - 0FH) Bank 2 with addresses (10H - 17H) Bank 3 with addresses (18H - 1FH)
				Overflow flag. Hardware is set or cleared during execution of arithmetic instructions to indicate an overflow condition		Hardware or software
				Spare. Contains a read / write trigger that can be used
				Parity bit. Hardware cleared or set in each instruction cycle to indicate an even or odd number of battery bits in the "1" state.		Hardware or software

Pointer stack SP - 8-bit register, the contents of which are incremented before writing data to the stack when executing the PUSH and CALL commands. On initial reset, the stack pointer is set to 07H, and the stack area in data RAM starts at 08H. If necessary, by redefining the stack pointer, the stack area can be located anywhere in the internal data RAM of microcontrollers.

Pointer data DPTR consists of high byte (DPH) and low byte

(DPL). Contains a 16-bit address when accessing external memory. Can be used

be written as a 16-bit register or as two independent eight-bit registers.

Port0 - PortZ. Separate bits of the special function registers P0, P1, P2, P3 are bits - "latches" of the ports P0, P1, P2, P3.

Buffer consistent port SBUF is two separate registers: the transmitter buffer and the receiver buffer. When data is written to SBUF, it enters the transmitter buffer, and writing a byte to SBUF automatically initiates its transmission over the serial port. When data is read from SBUF, it is fetched from the receiver buffer.

Registers timer. Register pairs (TH0, TL0) and (TH1, TL1) form 16-

bitwise counting registers for timer / counter 0 and timer / counter 1, respectively.

Registers management. Registers of special functions IP, IE, TMOD, TCON, SCON and PCON contain control bits and status bits of the interrupt system, timer

meters / counters and serial port. They will be discussed in detail below.

RxD TxD INT0 INT1 T0 T1 WR

P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

RST BQ2 BQ 1 EA

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

When operating, MK provides:

the minimum time for executing addition commands is 1 μs;

hardware multiplication and division with a minimum execution time of 4 μs.

The MK provides the ability to set the frequency of the internal oscillator using a quartz, LC-chain or an external oscillator.

The extended instruction system provides byte and bitwise addressing, binary and binary-decimal arithmetic, overflow indication and even / odd parity, and the possibility of implementing a logical processor.

The most important and distinctive feature of the architecture of the MCS51 family is that the ALU can manipulate single-bit data in addition to performing operations on 8-bit data types. Individual software-accessible bits can be set, cleared or replaced by their complement, can be sent, checked and

Figure 3.2. External conclusions

microcontroller

used in logical computing. Whereas support for simple data types (with existing

the trend towards increasing word length) may at first glance seem like a step backwards, this quality makes the MCS51 family of microcontrollers especially suitable for applications in which controllers are used. The algorithms of the latter, in their own way, assume the presence of input and output Boolean variables, which are difficult to implement using standard microprocessors. All of these properties are collectively referred to as the MCS51 Boolean processor family. With such a powerful ALU, the MCS51 family of instructions is equally well suited for real-time control applications and data-intensive algorithms.

The schematic diagram of the microcontroller is shown in Fig. 3.2. In the basic version, it is packaged in a 40-pin DIP package. Let's consider the purpose of the conclusions.

Let's start with the power pins «0 V" and "5 V" , for which he receives the main food. Consumption current is given in table. 3.1.

Output "RST" - reset of the microcontroller. When an active high level is applied to this pin, mode common dumping and MK performs the following actions:

Sets the PC command counter and all special function registers, except for the P0-P3 port latches, the SP stack pointer, and the SBUF register, to zero;

the stack pointer is set to 07H;

disables all interrupt sources, timer-counters and serial

selects BANK 0 RAM, prepares ports P0-P3 for receiving data and determines

separates ALE and PME pins as inputs for external synchronization;

in the special function registers PCON, IP and IE, spare bits are randomized, and all other bits are set to zero;

the SBUF register is set to random values.

sets the latches-latches of ports P0-P3 to "1".

The states of the microcontroller registers after reset are shown in Table 3.5.

Table 3.5.

	Information
	Indefinite
	0ХХХ0000В for k-MOS 0XXXXXXXB for n-MOS

The RST pin also has an alternative function. Through it, backup power is supplied to keep the contents of the microcontroller's RAM unchanged when the main one is removed.

conclusions BQ1, BQ2 – designed to connect a quartz resonator, which determines the clock frequency of the MK.

Output EA` (E xternal A dress – external address) - designed to activate the mode of reading control codes from the external program memory, when an active low level is applied to this output. The pin has an alternative purpose (function). It is supplied with the voltage of programming the EPROM in the programming mode.

Output PME (P rogram M emory E nable – permission memory programs) - designed to control the reading cycle from the program memory and is automatically activated by the MC in each machine cycle.

Output Ale (A dress L ength E nable – permission junior addresses) strobes the output of the lower part of the address on port P0. The output is also used when programming the EPROM, while a strobe pulse is supplied to it.

MK contains four groups of ports: P0, P1, P2, and P3. These are the rest of the 40 pins of the microcontroller. These ports can serve for bit-by-bit I / O information, but apart from this, each of them has its own specialization. The generalized functional diagram of the port is shown in Fig. 3.3. The port contains the output FET switches connected to the pin, the function switch, the latch on the D-flip-flop, and the control logic. The latch on the internal bus MK can be written one or zero. This information goes through the function switch to the output keys and the MK output. In the state of one, both transistors N and N1 are off, but N2 is on. In the state of zero, N opens

Xia, and N2 closes. At the moment when the port performs the alternative function for which it is specialized, the pin state is released. The microcontroller can separately read the state of the port latch and the state of its output, set by an external signal. For this in the assembler MK there are special commands that activate the corresponding lines. To read the pin state, the corresponding port latch must

be pre-recorded

From internal

Latch control

Function selector

Vcc

Weekends

unit. When the "read latch" line is activated at the output of the "AND" cell to which this line is connected, the

it tires MK D Q

Latch write C Q

Reading the latch

Port pin

the state of the latch, which is supplied to the internal bus of the MC, is activated when

"Read output" - the state of the external output of the port.

Port P0 - universal bi-directional port

input-output. Beyond this port

the function of organizing external address buses and

Rice. 3.3. Functional diagram of the microcontroller port

data for expanding program memory and data memory

microcontroller. When there is an access to external program memory or a command to access external data memory is executed, the lower part of the address (A0 ... A7) is set on the port pins, which is gated high on the ALE pin. Then, when writing to the data memory, the recorded information from the internal bus of the MC is fed to the pins of the P0 port. In read operations, on the contrary, information from the port pins goes to the internal bus. A feature of the P0 port is the absence of a "pull-up" transistor N2, which provides power to the output. Writing to the latch of the unit port simply puts it in a high impedance state, which is necessary for normal data bus operation. If it is necessary to power any external devices through the output, you should provide external resistors from the power supply circuits to the port output.

Port Р1 - universal bidirectional I / O port without alternative functions.

Port P2 - a universal bidirectional I / O port, as an alternative function, performing the issuance of the senior part of the address (A8 ... A15) when accessing external memory.

Port P3 - universal bidirectional input-output port, each bit of which provides for the implementation of various alternative functions. In this case, the alternative functions are implemented only if ones are written to the port pin latches, otherwise the execution of the alternative functions is blocked. Let's list them separately for each bit:

P3.0 – RxD (R ead e X ternal D ate, read external data) - input of the built-in serial transceiver.

P3.1 – TxD (T ype e X ternal D ate, transmit external data) - output of the built-in serial transceiver.

P3.2 – INT0` (INT errupt, interrupt) - external interrupt input 0.

P3.3 – INT1` - external interrupt input 1.

P3.4 – C / T0 - input of the zero built-in timer / counter.

P3.5 – C / T1 - input of the first built-in timer / counter.

P3.6 – WR` (W rite, write) - control output of the write cycle in data memory.

P3.7 – RD` (R ead, read) - output control of the read cycle from data memory.

The pins of port P1, P2 and P3 are capable of delivering current about 0.2mA in one unit and receiving a current of 3 mA at zero, the pins of port P0 are more powerful and capable of delivering a current of about 0.8mA per unit and receiving a current of 5 mA at zero. Brief information on the purpose of the microcontroller pins is given in table 3.6.

Table 3.6.

	Designation	Pin assignment
		8-bit bi-directional port P1. Address input A0-A7 when checking the internal ROM (EPROM)	enter exit
		General reset signal. Output of the backup RAM power from an external source (for 1816)
		8-bit bi-directional P3 port with additional functions	enter exit
		Receiver Serial Data - RxD
		Transmitter Serial Data - TxD
		External interrupt input 0- INT0`
		External interrupt input 1-INT1`
		Timer / Counter 0 input: - T0
		Timer / Counter 1 Input: - T1
		Strobe signal output when writing to external data memory: - WR`
		Strobe signal output when reading from external data memory - RD`
		Leads for connecting a quartz resonator.	exit entrance
		General conclusion
		8-bit bidirectional P2. Address output A8-A15 in the mode of operation with external memory. In the internal ROM check mode, pins P2.0 - P2.6 are used as an input of the address A8-A14. Conclusion P2.7 - permission to read ROM.	enter exit
		Program memory resolution
		Address latching enable output signal. When programming EPROM signal: PROG	enter exit
		Blocking of work with internal memory. When programming the EPROM, the UPR signal is given	enter exit
		8-bit bidirectional P0 port. Address / data bus r work with external memory. Data output D7-D0 in the mode of checking the internal ROM (EPROM).	enter exit
		Power output from + 5V voltage source

The basis of the microcontroller (see Fig. 1) is an 8-bit Arithmetic-Logic Unit (ALU). MK memory has Harvard architecture, i.e. logically divided: into program memory - PP (internal or external), addressed by a 16-bit command counter (SC) and data memory - internal (Resident data memory - RPD) 128 (or 256) bytes, as well as external (External data memory - VPD) up to 64 KB. Physically, program memory is implemented on ROM (read-only), and data memory - on RAM (data can be written and read).

Reception and delivery of external signals is carried out through 4 eight-bit ports P0..P3. When accessing external program memory (EPM) or data memory (EPM), ports P0 and P2 are used as a multiplexed external address / data bus. P3 port lines can also perform alternative functions (see Table 1).

The 16-bit DPTR register forms the VFD address or the base address of the Program Memory in the Accumulator conversion command. The DPTR register can also be used as two independent 8-bit registers (DPL and DPH) for storing operands.

8-bit internal command register (RK) receives the code of the command being executed; this code is decoded by the control circuit, which generates control signals (see Fig. 1).

Referring to the registers of special functions - RSF (SFR - in Fig. 1 they are circled with a dotted line) is possible only using direct byte addressing in the address range from 128 (80h) and more.

The resident data memory (RPM) in the first models of MCS-51 microcontrollers had a volume of 128 bytes. The lowest 32 bytes of the RPD are also general-purpose registers - RON (4 banks of 8 RONs). The program can address one of the 8 RONs of the active bank. The selection of the active RON bank is carried out by programming two bits in the processor status register - PSW.

Table 1 - Purpose of MCS-51 pins

Pin no.	Designation	Appointment
1..8	Р1	8-bit quasi-bidirectional input / output port
9	RST	Reset signal (active level - high); The RST signal clears: the PC and most of the Special Function Registers (SFRs), disabling all interrupts and timer operation; selects Bank RONs 0; writes "all ones" to ports P0_P3, preparing them for input; writes code 07H to the stack pointer (SP);
10..17		8-bit quasi-bidirectional input / output port; after writing to the corresponding category "1" - performs additional (alternative) functions: Serial port input - RxD; Serial port output - TxD; External interrupt input 0 - ~ INT0; External interrupt input 1 - ~ INT1; Timer / counter input 0 - T0; Timer / counter input 1 - T1; Strobe output. signal when writing to VPD - ~ WR; Strobe output. signal when reading from VPD - ~ RD;
18, 19	X1, X2	Leads for connecting a quartz resonator or LC-circuit;
20	GND	General conclusion;
21..28	P2	8-bit quasi-bidirectional input / output port; or the output of address A in the mode of operation with external memory (VFP or VFD);
29	PME	The strobe of reading the External Program Memory, is issued only when accessing the external ROM;
30	Ale	External memory address strobe (VPP or VPD);
31	EA	Switching off the RPP, level "0" at this input transfers the MC to a selection of commands only from runway ;
39..32	P0	8-bit bidirectional input / output port; when accessing the External Memory, it issues addresses A (which are written to the external register by the ALE signal), and then exchanges a byte synchronously with the signal ~ PME (for commands) or ~ WR, ~ RD (for data in VFD), when accessing External Memory all units are written to the port register P0, destroying the information stored there;
40	Ucc	Supply voltage output

Switching RON banks simplifies the execution of subroutines and interrupt handling, since there is no need to push the contents of RONs of the main program onto the stack when calling a subroutine (it is enough to go to another active bank of RONs in the subroutine).

The access to the RPD is possible using indirect or direct byte addressing (direct byte addressing allows accessing only the first 128 bytes of the RPD).

The extended RPD area (for microcontrollers of the MCS-52 family and subsequent families) from address 128 (80h) to 255 (FFh) can only be addressed using the indirect addressing method.

Table 2 - Block of Registers of Special Functions (s f r)

	Mnemo code	Name
0E0h	* ACC	Battery
0F0h	* B	Battery expander register
0D0h	* PSW	Processor Status Word
0B0h	* P3	Port 3
0A0h	* P2	Port 2
90h	* P1	Port 1
80h	* P0	Port 0
0B8h	* IP	Interrupt Priority Register
0A8h	* IE	Interrupt mask register
99h	SBUF	Serial transceiver buffer
98h	* SCON	Serial Port Control / Status Register
89h	TMOD	Timer / Counter Mode Register
88h	* TCON	Timer / counter control / status register
8Dh	TH1	Timer 1 (high byte)
8Bh	TL1	Timer 1 (Low Byte)
8Ch	TH0	Timer 0 (high byte)
8Ah	TL0	Timer 0 (low byte)
83h	DPH	Data Pointer Register (DPTR) (High Byte)
82h	DPL	Data Pointer Register (DPTR) (Low Byte)
81h	SP	Stack pointer register
87h	PCON	Power consumption control register

2. SOFTWARE MODEL MCS – 51

COMMAND TYPES MCS – 51

Almost half of the instructions are executed in 1 machine cycle (MC). With a crystal oscillator frequency of 12 MHz, the execution time of such a command is 1 μs. The rest of the commands are executed in 2 machine cycles, i.e. for 2 μs. Only the instructions for multiplication (MUL) and division (DIV) are executed in 4 machine cycles.

During one machine cycle, there are two calls to the Program Memory (internal or external) to read two command bytes or one access to the External Data Memory (EPM).

3. METHODS (METHODS) OF ADDRESSING MCS-51

1. REGISTER ADDRESSING - the 8-bit operand is in the RON of the selected (active) bank of registers;

2 DIRECT ADDRESSING (denoted by - #) - the operand is in the second (and for a 16-bit operand and in the third) byte of the command;

3 INDIRECT ADDRESSING (denoted by - @) - the operand is in the Data Memory (RPD or VPD), and the address of the memory cell is contained in one of the RONs of indirect addressing (R0 or R1); in the PUSH and POP commands, the address is contained in the SP stack pointer; DPTR register can contain up to 64K VPD address;

4 DIRECT BYTE ADDRESSING - (dir) - is used to access the cells of the RPD (addresses 00h… 7Fh) and to the registers of special functions SFR (addresses 80h… 0FFh);

5 DIRECT BIT ADDRESSING - (bit) - is used to refer to separately addressable 128 bits located in the RPD cells at addresses 20H ... 2FH and to separately addressable bits of special functions registers (see Table 3 and the program model);

6 INDIRECT INDEX ADDRESSING (denoted by - @) - simplifies viewing tables in the Program Memory, the PP address is determined by the sum of the base register (PC or DPTR) and the index register (Accumulator);

7 IMPACT (BUILT-IN) ADDRESSING - the command code contains an implicit (by default) reference to one of the operands (most often to the Battery).

4. PROCESSOR STATE WORD FORMAT (PSW)

C - Carry flag (CARY) or borrow, also serves as a "Boolean Accumulator" in instructions that operate on bits;

AC - auxiliary (additional) carry flag - set to "1" if in the addition command (ADD, ADDC) there was a transfer from the lower nibble to the higher one (ie from the 3rd bit to the 4th bit);

F0 - user flag - set, cleared and checked programmatically;

RS1	RS0	Bank	Address (dir)
0	0	0	00h..07h
0	1	1	08h..0Fh
1	0	2	10h..17h
1	1	3	18h..1Fh

RS1, RS0 - Register bank selection:

OV - Arithmetic overflow flag; its value is determined by the "Exclusive OR" operation of the signals of the input and output carries of the most significant bit of the ALU; a single value of this flag indicates that the result of an arithmetic operation in a two's complement code is out of range: –128… + 127; when performing a division operation, the OV flag is cleared, and in the case of division by zero, it is set; when multiplying, the OV flag is set if the result is greater than 255 (0FFH);

Bit PSW - Reserved, contains a flip-flop, available for writing or reading;

P - parity flag - is the complement of the number of single bits in the accumulator to even; formed by a combinational circuit (software available only by reading).

There is no "Z" flag in MCS-51 microcontrollers. But in the conditional jump instructions (JZ, JNZ), the current (zero or non-zero) contents of the Accumulator are checked by the combinational circuit.

All commands for transferring and exchanging operands can be carried out via the Battery (see Fig. 3). Moreover, transfers from / to External Memory (Program Memory or Data Memory) can be carried out only through the Battery.

Most transfers can also be done via a direct address byte (dir). There are even dir-dir forwards (see Figure 3).

Missing transfers from RON to RON can be implemented as transfers from RON to a directly addressable byte dir (taking into account that RONs are located in the initial area of ​​the Resident Data Memory, the cells of which can be addressed as dir).

The XCH exchange commands allow the transfer of bytes without destroying both operands.

Arithmetic commands are only executed in the Accumulator. Therefore, the first operand must first be placed in the Accumulator and then add or subtract the second operand. The result is placed in the Battery.

The subtract SUBB command is performed only with a borrow (i.e., the Сary flag is also subtracted from the result). Therefore, to execute the subtraction command without borrowing, you must first execute the command to clear the C flag (CLRC).

The instruction for multiplying single-byte operands - MULAB - places a two-byte (16 bit) result: the low byte - in the Battery, the high byte - in the register B.

The result of executing the command for dividing single-byte operands - DIVAB - is placed: quotient - a Accumulator, the remainder - into register B.

The INC arithmetic instruction adds one to the selected operand. The DEC arithmetic instruction subtracts one from the selected operand. The Decimal Accumulator Correction (DAA) command helps you add binary-decimal numbers (BCD numbers) without converting them to hexadecimal format (hex format). The source operands must be in BCD format, i.e. each tetrad of one byte contains only numbers from 0 to 9 (there cannot be hexadecimal numbers: A, B, C, D, E, F). Therefore, one byte can contain numbers from 00 to 99 for packed BCD numbers, or numbers from 0 to 9 for unpacked BCD numbers.

The DA A - decimal correction command performs actions on the contents of the Accumulator after the addition of BCD numbers in the processor (the numbers were added according to the laws of hexadecimal arithmetic) as follows (see example):

· If the contents of the lowest nibble of the Accumulator is greater than 9 or the auxiliary carry flag is set (AC = 1), then 6 is added to the contents of the Accumulator (i.e. the missing six digits in hex format);

· If after that the content of the Accumulator's high nibble is greater than 9 or the C flag is set, then the number 6 is added to the Accumulator's high nibble.

The DA A decimal offset command is not used after the INC command because the increment command does not affect (change) the C and AC flags.

Logical commands:

Logical "AND" - ANL,

Logical "OR" - ORL,

The logical command "EXCLUSIVE OR" - XRL– are executed in the Accumulator (as well as arithmetic), but it is possible to execute logical commands also in the direct addressable byte (dir). In this case, the second operand can be:

In the Battery or

The immediate operand in the command.

Rotation commands (RR A, RL A) and rotation commands through the CARY flag (RRC A, RLC A) cyclically shift the contents of the Accumulator by 1 bit. Bit device references are carried out only through the C flag.

Ministry of General and Professional Education of the Russian Federation Novosibirsk State Technical University V.N. Veprik, V.A. Afanasyev, A.I. Druzhinin, A.A. Zemskov, A.R. Isaev, O. V. Malyavko MICROCONTROLLERS OF THE MCS-51 FAMILY Textbook on the courses "Microprocessor systems" and "Design of microprocessor systems" for senior students of the Faculty of Automation and Computer Engineering of all forms of education Novosibirsk 1997 V.N. Veprik, V.A. Afanasyev, A.I. Druzhinin, A.A. Zemskov, A.R. Isaev, O. V. Malyavko. Microcontrollers MCS-51 Family: Tutorial. - Novosibirsk. This tutorial contains a general description of the architecture, functionality and instruction set of the MCS-51 family of single-chip microcontrollers (Embedded Microcontrollers) manufactured by INTEL. The second part of the manual provides a description of the educational microprocessor controller UMPK-51, offered to students as an object of research when performing a cycle of laboratory work. The material of the manual can be used in coursework and diploma design, and can also be useful for circuit engineers involved in the development and operation of electronic equipment. The authors express their deep gratitude to AOZT "New Technologies" - the official distributor of INTEL for providing the materials on the basis of which this work was performed. Table 15, fig. 25, list of lit. 12 titles Reviewers: E.D. Baran, G.G. Matushkin. The work was prepared at the Department of Computer Engineering Novosibirsk State © Technical University 2 INTRODUCTION. The MCS-51 family of 8-bit single-chip microcontrollers entered the global market in the early eighties. The first modifications of the crystals (about 7) were made using high-quality n-MOS (HMOS) technology and were functionally complete single-chip microcomputers of the Harvard architecture, one of the main principles of which is the logical separation of the address spaces of program memory and data. With the development of semiconductor technology, subsequent versions of MCS-51 microcircuits began to be manufactured using more advanced and low-power CMOS (CHMOS) technology (in active mode, the consumption of crystals was brought to 10-50 mA). The MCS-51 command system, focused on the implementation of various digital control algorithms, while maintaining some external similarity with the command system of the previous MCS-48 family, has qualitatively expanded, fundamental innovations have appeared in it: bit-oriented operations and bit fields addressable in data memory, which made it possible to talk about the implementation of a bit processor on a chip; Implemented execution of multiplication, division and subtraction commands; improved work with the stack; the group of control transfer commands has been expanded; The command system began to look more symmetrical, that is, less dependent on data transfers through the battery. The functionality of the built-in peripherals has also been expanded with the introduction of: two 16-bit timers / counters; hardware serial duplex port; two-level interrupt system; four 8-bit I / O ports. Fundamental changes in the structure of the time cycle of the processor have led to the acceleration of work with external memory of programs and data, as well as reactions to external and internal interrupts. The total size of the address space of the external program and data memory has increased to 128 KB. The 16-bit registers of the Program Counter and Data Pointer allowed direct access to the entire address range, which gave developers the ability to implement algorithms for fast processing of large data arrays. All software-accessible nodes of the microcontroller were brought together in a special area of ​​data memory (Special Function Register), which made it possible to access them in almost the same way as to ordinary cells of resident RAM. In later modifications of crystals, the improvement went along the path of increasing additional functionality while maintaining full software compatibility with earlier versions. The features of the latest modifications of MCS-51 microcontrollers are: completely static design; 3- and 5-volt crystal versions; wide range of built-in peripherals; maximum clock frequency - 24 MHz; for individual groups of crystals - 33 MHz. Currently, the MCS-51 includes about 60 versions of crystals, in addition, there is and is available detailed proprietary documentation (unfortunately, so far little translated into Russian). To prepare the software for MCS-51 microcontrollers, the languages ​​"ASM-51", "C" are mainly used, for which there are a number of well-proven compilers, libraries of standard subroutines and software emulators produced by various foreign and domestic firms. 3 Despite the sufficient "antiquity" of the family (more than 15 years) and the appearance on the world market in recent years of single-chip microcontrollers of higher performance and improved architecture - MCS-51, MCS-251, MCS-96, MCS-51 controllers will be widely used in relatively simple embedded control systems. 4 1. DESIGNATION SYSTEM OF INTEL COMPONENTS AND FUNCTIONAL COMPOSITION OF THE MCS-51 FAMILY For marking microcircuits by INTEL, a designation system of several fields is used: 1 2 3 4 ХХ ХХХХХХХХХХХХХХХ ХХХХХХ The first field contains a one-letter temperature prefix Automotive: , automotive version for an extended temperature range (-40 / + 125 C) M (Military), version according to military standards (-55 / + 125 C) Q or C (Commercial), "commercial" temperature range (0 / + 70 C ) s (160 8) - one hour dynamic thermal training; L or E (Extended), "extended" temperature range (-40 / + 85 C) with (160 8) - hour dynamic thermal training; T (Extended), "extended" temperature range (-40 / + 85 C) without thermal training; I (Industrial), execution according to industrial standards. The second field contains a one- or two-letter prefix indicating the package type of the microcircuit (Package Type). There are several dozen different types of microcircuit packages today, therefore, as an example, we will give only some designations: A Ceramic Pin Grid Array, (PGA); C Ceramic Dual In-Line Package, (CDIP); K Ceramic Quad Flatpack Package, (QFP); KD Plastic Quad Flatpack Package, Fine Pitch, Die Down, (PQFP); KU Plastic Quad Flatpack Package, Fine Pitch, Die Up, (PQFP); N Plastic Leaded Chip Carrier, (PLCC); P Plastic Dual In-Line Package, (PDIP); SM Single In-Line Leadless Memory Module, (SIMM); U Plastic Dual In-Line Package, Shrink Dip, (PDIPS); Z Zigzag In-Line Package, (ZIP). The third field can contain up to 15 numeric and alphabetic characters indicating the type of a specific device located on the chip. The fourth field can include up to six digital and alphabetic characters, reflecting various features and versions of microcircuits. Additional information on the types of packages and their design can be found in the book: Packaging Order Number 240800. With regard to the described microcontrollers of the MCS-51 family, the first character of the third field is traditionally (for Intel) equal to "8". The second character of the third field usually indicates the type of built-in ROM: 0 masked ROM of programs; crystal without ROM (for later versions of crystals); 1 mask ROM of programs (Standard ROM Code, Firmware); 3 mask ROM (for later crystal versions), (Customizable ROM Code); 7 UVROM or one-time programmable ROM (EPROM or OTP ROM); 8 EEPROM (Flash - memory on a chip) Further, a letter may follow, indicating the technological features of manufacturing: no letter HMOS technology, power supply 5V; With CHMOS technology, 5V power supply; L CHMOS technology, power supply 3V; 5 The next characters of the third field for MCS-51 microcontrollers are numbers (for example, 31,32,51,54,58,152) and from one to four letters, which reflect the functional features of the crystals (for example, ROM size, specifics of a group of crystals, system availability protection of program memory from unauthorized access, the ability to use a more advanced programming algorithm "Quick Pulse" and the like). In the original technical documentation of Intel, all MCS-51 microcontrollers are grouped into groups ("Product Line"), each of which unites the crystal versions closest in their functionality and electrical parameters. Since the names of microcircuits of one group differ insignificantly, to designate each individual group, a generalized symbolism is used, formed from the marking of specific microcircuits, by replacing the differing characters with "X". Thus, the following groups of microcontrollers can be distinguished. 1. Group 8Х5Х (8051 Product Line and 8052 Product Line): 8031АН, 8051АН, 8751Н, 8051АНР, 8751Н-8, 8751ВН, 8032АН, 8052АН, 8752ВН. 2. Group 8ХС51 (80С51 Product Line): 80С31ВН, 80С51ВН, 87С51. 3. Group 8ХС5Х (8ХС52 / 54/58 Product Line): 80С32, 80С52, 87С52, 80С54, 87С54, 80С58, 87С58. 4. Group 8XC51FX (8XC51FA / FB / FC Product Line): 80C51FA, 83C51FA, 87C51FA, 83C51FB, 87C51FB, 83C51FC, 87C51FC. 5. Group 8ХL5X (8XL52 / 54/58 Product Line): 80L52, 87L52, 80L54, 87L54, 80L58, 87L58. 6. Group 8XL51FX (8XL51FA / FB / FC Product Line): 80L51FA, 83L51FA, 87L51FA, 83L51FB, 87L51FB, 83L51FC, 87L51FC. 7. Group 8XC51RX (8XC51RA / RB / RC Product Line): 80C51RA, 83C51RA, 87C51RA, 83C51RB, 87C51RB, 83C51RC, 87C51RC. 8. Group 8XC51GB (8XC51GX Product Line): 80C51GB, 83C51GB, 87C51GB. 9. Group 8XC152JX (8XC152 Product Line): 80C152JA, 83C152JA, 80C152JB, 80C152JC, 83C152JC, 80C152JD. 10.Group 8XC51SL (8XC51SL Product Line): 80C51SL-BG, 81C51SL-BG, 83C51SL-BG, 80C51-AH, 81C51SL-AH, 83C51SL-AH, 87C51SL- AH, 80C51SL-AL, 81C51SL-AL, 83C51 87C51SL-AL. The first group of microcontrollers includes junior models of the family, made using n-MOS technology and not recommended for use in new designs, all other groups are made using modern CMOS technology. Microcircuits of the second, third and fourth groups are today the classic representatives of the MCS-51 family. The fifth and sixth groups include 3-volt versions of crystals (Low-Voltage). Crystals of the seventh group are equipped with expanded RAM (Expanded RAM), the volume of which is 512 bytes. Microcircuits of the eighth, ninth and tenth groups are application-specific microcontrollers (Application Specific). Many modern applications require high-performance MCUs that use advanced addressing capabilities, register architecture, large amounts of internal RAM and stack, and efficiently support high-level programming. These microcontrollers include the New Architecture MCS-5 and MCS-251 microcontrollers, which Intel began production in 1995. The functional composition and key features of the MCS-51 / MCS-251 microcontroller are given in the appendix. 6 2. BASIC CHARACTERISTICS OF THE BASIC MODEL OF THE FAMILY OF MICROCONTROLLERS MCS-51. The base model of the MCS-51 family of microcontrollers and the basis for all subsequent modifications is the I-8051 microcontroller. Its main features are as follows: an eight-bit CPU optimized for control functions; built-in clock generator; address space of program memory - 64 K; data memory address space - 64 K; internal program memory - 4K; internal data memory - 128 bytes; additional possibilities for performing Boolean algebra operations (bitwise operations); 32 bidirectional and individually addressable I / O lines; 2 sixteen-bit multifunctional timers / counters; full duplex asynchronous transceiver; vector interrupt system with two priority levels and six event sources. The block diagram of the I-8051 is shown in Fig. 1, the pin assignment of the microcircuit is shown in Fig. 2. External interrupts Interrupts 128 bytes T / C 0 counter 4K ROM control RAM T / C 1 inputs CPU BUS 4 I / O Serial OSC control Ports Port P0 P1 P2 P3 T D R D Address / Data Fig. 1. I-8051 block diagram The entire MCS-51 series has a Harvard architecture, that is, separate address spaces for program and data memory. The memory organization is shown in Fig. 3. The amount of internal (resident) program memory (ROM, EPROM or OTP ROM) located on the chip, depending on the type of microcircuit, can be 0 (ROMless), 4K (base crystal), 8K, 16K or 32K. If necessary, the user can expand the program memory by installing an external ROM. Access to the internal or external ROM is determined by the value of the signal at the EA pin (External Access): EA = Vcc (supply voltage) - access to the internal ROM; EA = Vss (ground potential) - access to external ROM. For crystals without ROM (ROMless), the EA pin must be permanently connected to Vss. The external ROM read strobe - PS EN (Program Store Enable) is generated when accessing the external program memory and is inactive when accessing the ROM located on the chip. 7 The area of ​​the lower addresses of the program memory is used by the interrupt system, the architecture of the 8051 microcircuit provides support for five sources of interrupts: two external interrupts; two interrupts from timers; interrupts from the serial port. P1.0 1 40 Vcc P1.1 2 39 P0. 0 (AD0) P1.2 3 38 P0.1 (AD1) P1.3 4 37 P0.2 (AD2) P1.4 5 36 P0.3 (AD3) P1.5 6 35 P0.4 (AD4) P1. 6 7 34 P0.5 (AD5) P1.7 8 33 P0.6 (AD6) RESET 9 32 P0.7 (AD7) (RD) P3.0 10 31 EA / Vpp (TD) P3.1 11 30 ALE / PROG (INT0) P3.2 12 29 PSEN (INT1) P3.3 13 28 P2.7 (A15) (T0) P3.4 14 27 P2.6 (A14) (T1) P3.5 15 26 P2.5 ( A13) (WR) P3.6 16 25 P2.4 (A12) (RD) P3.7 17 24 P2.3 (A11) XTAL2 18 23 P2.2 (A10) XTAL1 19 22 P2.1 (A9) Vss 20 21 P2.0 (A8) Fig. 2. Pin assignment I-8051 Program memory (Read) Data memory (Read / Write) FFFFH External ROM FFFFH External @DPTR RD memory PSEN WR data @PC MOVC EA = 0 Internal memory @DPTR data @PC External internal FFH upper 128 SFR MOVX ROM ROM 80H EA = 0 0000H EA = 1 lower 128 00H 0000H PSEN Fig. 3. MCS-51 Family Memory Organization 8 Figure 4 shows a map of the lower program memory area. ROM Program memory 0033H 002BH Serial Port 0023H Vector Timer1 001BH interrupts EINT1 0013H Timer0 000BH EINT0 0003H Start address 0000H (Reset) Fig. 4. Program memory The addresses of the interrupt vectors are located at intervals of 8 bytes: - 0003H external interrupt 0 (External Interrupt 0) - pin IN T 0; - 000BH interrupt from timer 0 (by the timer overflow flag - T F 0); - 0013H external interrupt 1 - pin IN T 1; - 001BH interrupt from timer 1 (by the timer overflow flag - T F 1); - 0023H interrupt from the serial port (Serial Interrupt = Receive Interrupt or Transmit Interrupt); etc. The data memory is separate from the program memory. 64K external RAM addressing is possible in this area. When accessing the external data memory, the microcontroller's CPU generates the corresponding read (R D) or write (W R) signals, interaction with the internal data memory is carried out at the command level, while the R D and W R signals are not generated. External program memory and external data memory can be combined by ANDing the R D and PS EN signals to provide an external memory (program / data) strobe. The lower 128 bytes of internal data memory (lower 128) are present on all MCS-51 dies and are shown in Figure 5. The first 32 bytes represent 4 banks (Register Bank) with 8 registers (R7 ... R0). Registers R0 and R1 in any of the banks can be used as indirect address registers. The 16 bytes following the register banks form a block of bit-addressable space. The MCS-51 instruction set contains a wide variety of bit operations, and the 128 bits in this block are directly addressable and the addresses range from 00H to 7FH. All bytes in the lower 128-byte half of the memory can be addressed directly or indirectly. The upper 128 byte half of the RAM memory (upper 128) is absent in the I-8051 chip, but it is available in the versions of crystals with 256 bytes of RAM. In this case, the "Upper 128" area is only available for indirect addressing. The SFR (Special Function Register) area is only available with direct addressing. The arrangement of the special function registers in the SFR space is shown in Fig. 6. These include port registers, timers, peripheral controls, and so on. 9 7FH Byte-addressable RAM area 30H (direct, indirect) 2FH 7FH 7EH 7DH 7CH 7BH 7AH 79H 78H 2EH 77H 76H 75H 74H 73H 72H 71H 70H Byte-addressable RAM area (direct) 21H 0FH 0EH 0DH 0CH 0BH 20AH 09H 08H 06H 05H 04H 03H 02H 01H 00H 1FH RB3 18H 17H RB2 10H 0FH RB1 08H 07H SP after RESET 00H RB0 (R7 + R0) Fig. 5. Bottom 128 bytes of internal RAM. bit addressing 8 bytes F8H FFH F0H B F7H E8H EFH E0H ACC E7H D8H DFH D0H PSW D7H C8H CFH C0H C7H B8H IP BFH B0H P3 B7H A8H IE AFH A0H P2 A7H 98H SCONH SBH1 TM TH1 97 80H P0 SP DPL DPH PCO 87H N 0/8 1/9 2 / A 3 / B 4 / C 5 / D 6 / E 7 / F Fig. 6. Placement of special function registers in SFR space. For 16 addresses in the SFR space, both byte and bit addressing is possible. For bit-addressable registers, the hexadecimal address ends with "0H" or "8H". Bit addresses in this area range from 80H to FFH. The entire series of crystals of the MCS-51 family has a basic set of SFRs, as in the I-8051 microcircuit, located at the same addresses. However, in crystals, which are a further development of the family in the SFR region, new registers are added to expand 10

The OMEVM command system provides great data processing capabilities, provides the implementation of logical, arithmetic operations, as well as real-time control. Bitwise, tetrad (4 bits), byte (8 bits) and 16-bit data processing are implemented.

LSI family MCS-51 - 8-bit ОМЭВМ: ROM, RAM, special purpose registers, ALU and external buses have a byte organization. The double-byte data is used only by the Pointer Register (DPTR) and the Command Counter (PC). It should be noted that the data pointer register can be used as a two-byte DPTR register or as two one-byte special purpose registers DPH and DPL. The command counter is always used as a two-byte register.

The OMEVM command set has 42 mnemonic designations of commands to concretize 33 functions of this system.

The syntax for most assembly language commands consists of a function mnemonic, followed by operands that indicate addressing methods and data types. The different data types or addressing modes are determined by the set operands, not by changes in mnemonic designations.

The command system can be conditionally divided into five groups:

The following types of addressing of source operands exist:

• Indirect register addressing by the sum of the base and index registers

Table of symbols and symbols used in the command system

Designation, symbol	Appointment
A	Battery
Rn	Registers of the currently selected register bank
r	The number of the loaded register specified in the command
direct	Directly addressable 8-bit internal data cell address, which can be an internal data RAM cell (0-127) or SFR (128-255)
@Rr	Indirectly addressable 8-bit cell of internal data RAM
data8	8-bit direct data included in the CPC
dataH	Most significant bits (15-8) of direct 16-bit data
dataL	The least significant bits (7-0) of direct 16-bit data
addr11	11-bit destination address
addrL	Least significant bits of the destination address
disp8	8-bit signed offset byte
bit	Direct addressable bit whose address contains the CPC located in the internal data RAM or SFR
a15, a14 ... a0	Destination address bits
(NS)	Content of element X
((NS))	Content at the address stored in element X
(X) [M]	Discharge M of element X
+ - * AND OR XOR / X	Operations: additions subtraction multiplication division logical multiplication (AND operation) logical addition (OR operation) addition mod 2 (exclusive OR) inversion of element X

Function mnemonics are uniquely associated with specific combinations of addressing methods and data types. A total of 111 such combinations are possible in the command system. The table provides a list of commands, sorted alphabetically.

Mnemonics	Function	Flags
ACALL command	Absolute subroutine call
	Addition	AC, C, OV
	Carry folding	AC, C, OV
AJMP Team	Absolute transition
	Logical "AND"
	Logical "AND" for variable bits	C
	Compare and jump if not equal	C
CLR A Command	Battery reset
CLR Command	Clearing a bit	C, bit
CPL Team A	Battery inversion
CPL Team	Bit inversion	C, bit
Team DA A	Accumulator decimal correction for addition	AC, C
DEC Team<байт>	Decrement
DIV AB Team	Division	C, OV
DJNZ Team<байт>, <смещение>	Decrement and transition if not zero
INC Team<байт>	Increment
INC DPTR Team	Data pointer increment
JB Team ,	Jump if bit is set
JBC Team ,	Jump if a bit is set and clear that bit
JC Team	Jump if carry is set
JMP @ A + DPTR Command	Indirect transition
JNB Team ,	Jump if bit is not set
JNC Team	Jump if carry is not set
JNZ Team	Jump if battery content is non-zero
JZ Team	Jump if accumulator content is 0
LCALL Command	Long call
LJMP Team	Long crossing
	Send byte variable
	Send data bit	C
MOV DPTR command, # data16	Load Data Pointer With 16-Bit Constant
MOVC command A, @ A + ( )	Send byte from program memory
	Send data to external memory (from external memory)